MTRR: get physical address size from CPUID

[coreboot.git] / src / cpu / intel / model_6fx / model_6fx_init.c

diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 3d2ca619bacc2ddbd6f57e96f902c18c2c351c89..033dfe6639ef78c1f83582d8347b127e01062f77 100644 (file)
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -28,9 +28,11 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/acpi.h>
 #include <cpu/intel/hyperthreading.h>
 #include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
+#include <cpu/x86/name.h>
 #include <usbdebug.h>
 
 static const uint32_t microcode_updates[] = {
@@ -58,38 +60,6 @@ static const uint32_t microcode_updates[] = {
         0x0, 0x0, 0x0, 0x0,
 };
 
-static inline void strcpy(char *dst, char *src)
-{
-       while (*src) *dst++ = *src++;
-}
-
-static void fill_processor_name(char *processor_name)
-{
-       struct cpuid_result regs;
-       char temp_processor_name[49];
-       char *processor_name_start;
-       unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
-       int i;
-
-       for (i=0; i<3; i++) {
-               regs = cpuid(0x80000002 + i);
-               name_as_ints[i*4 + 0] = regs.eax;
-               name_as_ints[i*4 + 1] = regs.ebx;
-               name_as_ints[i*4 + 2] = regs.ecx;
-               name_as_ints[i*4 + 3] = regs.edx;
-       }
-
-       temp_processor_name[48] = 0;
-
-       /* Skip leading spaces */
-       processor_name_start = temp_processor_name;
-       while (*processor_name_start == ' ')
-               processor_name_start++;
-
-       memset(processor_name, 0, 49);
-       strcpy(processor_name, processor_name_start);
-}
-
 #define IA32_FEATURE_CONTROL 0x003a
 
 #define CPUID_VMX (1 << 5)
@@ -126,15 +96,6 @@ static void enable_vmx(void)
 #define PMG_IO_BASE_ADDR       0xe3
 #define PMG_IO_CAPTURE_ADDR    0xe4
 
-/* MWAIT coordination I/O base address. This must match
- * the \_PR_.CPU0 PM base address.
- */
-#define PMB0_BASE              0x510
-
-/* PMB1: I/O port that triggers SMI once cores are in the same state.
- * See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
- */
-#define PMB1_BASE              0x800
 #define HIGHEST_CLEVEL         3
 static void configure_c_states(void)
 {
@@ -196,6 +157,19 @@ static void configure_misc(void)
 
        msr.lo |= (1 << 20);    /* Lock Enhanced SpeedStep Enable */
        wrmsr(IA32_MISC_ENABLE, msr);
+
+       // set maximum CPU speed
+       msr = rdmsr(IA32_PERF_STS);
+       int busratio_max=(msr.hi >> (40-32)) & 0x1f;
+
+       msr = rdmsr(IA32_PLATFORM_ID);
+       int vid_max=msr.lo & 0x3f;
+
+       msr.lo &= ~0xffff;
+       msr.lo |= busratio_max << 8;
+       msr.lo |= vid_max;
+
+       wrmsr(IA32_PERF_CTL, msr);
 }
 
 #define PIC_SENS_CFG   0x1aa
@@ -211,7 +185,7 @@ static void configure_pic_thermal_sensors(void)
        wrmsr(PIC_SENS_CFG, msr);
 }
 
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
 static unsigned ehci_debug_addr;
 #endif
 
@@ -229,7 +203,7 @@ static void model_6fx_init(device_t cpu)
        fill_processor_name(processor_name);
        printk(BIOS_INFO, "CPU: %s.\n", processor_name);
 
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
        // Is this caution really needed?
        if(!ehci_debug_addr)
                ehci_debug_addr = get_ehci_debug();
@@ -237,13 +211,13 @@ static void model_6fx_init(device_t cpu)
 #endif
 
        /* Setup MTRRs */
-       x86_setup_mtrrs(36);
+       x86_setup_mtrrs();
        x86_mtrr_check();
 
        /* Setup Page Attribute Tables (PAT) */
        // TODO set up PAT
 
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
        set_ehci_debug(ehci_debug_addr);
 #endif