/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
{
unsigned int cpu_reset = 0;
-#if USE_FALLBACK_IMAGE == 1
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- } else {
- /* This is the primary cpu how should I boot? */
- check_cmos_failed();
- if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- }
- normal_image:
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- );
- fallback_image:
-#endif
-
real_main(bist);
/* No servicable parts below this line .. */
- {
- /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
- unsigned v_esp;
- __asm__ volatile (
- "movl %%esp, %0\n\t"
- : "=a" (v_esp)
- );
- printk_spew("v_esp=%08x\r\n", v_esp);
- }
+#ifdef CAR_DEBUG
+ /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
+ unsigned v_esp;
+ __asm__ volatile (
+ "movl %%esp, %0\n"
+ : "=a" (v_esp)
+ );
+ printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
+#endif
cpu_reset_x:
- printk_spew("cpu_reset = %08x\r\n",cpu_reset);
-
- if(cpu_reset == 0) {
- print_spew("Clearing initial memory region: ");
- }
- print_spew("No cache as ram now - ");
+ printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
+ printk(BIOS_SPEW, "No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
::"a" (cpu_reset)
);
- if(cpu_reset==0) {
-#define CLEAR_FIRST_1M_RAM 1
-#include "cache_as_ram_post.c"
- } else {
#undef CLEAR_FIRST_1M_RAM
#include "cache_as_ram_post.c"
- }
+
+ /* For now: use rambase + 1MB - 64K (counting downwards) as stack. This
+ * makes sure that we stay completely within the 1M of memory we
+ * preserve with the memcpy above.
+ */
+
+#ifndef HIGH_MEMORY_SAVE
+#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
+#endif
__asm__ volatile (
- /* set new esp */ /* before _RAMBASE */
- "subl %0, %%ebp\n\t"
- "subl %0, %%esp\n\t"
- ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+ "movl %0, %%ebp\n"
+ "movl %0, %%esp\n"
+ :: "a" (CONFIG_RAMBASE + HIGH_MEMORY_SAVE)
);
{
/* get back cpu_reset from ebx */
__asm__ volatile (
- "movl %%ebx, %0\n\t"
+ "movl %%ebx, %0\n"
:"=a" (new_cpu_reset)
);
/* Copy and execute coreboot_ram */
copy_and_run(new_cpu_reset);
- /* We will not return */
}
- print_debug("sorry. parachute did not open.\r\n");
+ /* We will not return */
+ printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
}