1. This patch adds CAR for Intel P6 series processors.

[coreboot.git] / src / cpu / intel / model_6ex / cache_as_ram_disable.c

diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index fcdd3f2e19878cfd90bd33e953dd05b9dc696dc7..f859336adf75af12e6d8bde54a3f5c56180fb468 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -19,56 +19,33 @@
  * MA 02110-1301 USA
  */
 
-#include "cpu/x86/car/copy_and_run.c"
+#include <arch/stages.h>
 
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
 void real_main(unsigned long bist);
 
 void stage1_main(unsigned long bist)
 {
        unsigned int cpu_reset = 0;
 
-#if !defined(CONFIG_TINY_BOOTBLOCK) || !CONFIG_TINY_BOOTBLOCK
-#if CONFIG_USE_FALLBACK_IMAGE == 1
-        /* Is this a deliberate reset by the bios */
-        if (bios_reset_detected() && last_boot_normal()) {
-                goto normal_image;
-        } else {
-               /* This is the primary cpu how should I boot? */
-               check_cmos_failed();
-               if (do_normal_boot()) {
-                       goto normal_image;
-               }
-               else {
-                       goto fallback_image;
-               }
-       }
- normal_image:
-        __asm__ volatile ("jmp __normal_image"
-                : /* outputs */
-                : "a" (bist) /* inputs */
-                );
- fallback_image:
-#endif
-#endif
-
        real_main(bist);
 
        /* No servicable parts below this line .. */
-
-#if CAR_DEBUG
+#ifdef CAR_DEBUG
         /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
        unsigned v_esp;
        __asm__ volatile (
                "movl   %%esp, %0\n"
                : "=a" (v_esp)
        );
-       printk_spew("v_esp=%08x\n", v_esp);
+       printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
 #endif
 
-cpu_reset_x:
-
-        printk_spew("cpu_reset = %08x\n", cpu_reset);
-       printk_spew("No cache as ram now - ");
+        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
+       printk(BIOS_SPEW, "No cache as ram now - ");
 
        /* store cpu_reset to ebx */
         __asm__ volatile (
@@ -108,5 +85,5 @@ cpu_reset_x:
        }
 
        /* We will not return */
-       printk_debug("sorry. parachute did not open.\n");
+       printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
 }