1. This patch adds CAR for Intel P6 series processors.

[coreboot.git] / src / cpu / intel / model_6ex / cache_as_ram_disable.c

diff --git a/src/cpu/intel/model_6ex/cache_as_ram_disable.c b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
index cbf7cdd37b0df82e66d7e336a2bb8715fa7a1390..f859336adf75af12e6d8bde54a3f5c56180fb468 100644 (file)
--- a/src/cpu/intel/model_6ex/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6ex/cache_as_ram_disable.c
@@ -19,8 +19,12 @@
  * MA 02110-1301 USA
  */
 
-#include "cpu/x86/car/copy_and_run.c"
+#include <arch/stages.h>
 
+/* called from assembler code */
+void stage1_main(unsigned long bist);
+
+/* from romstage.c */
 void real_main(unsigned long bist);
 
 void stage1_main(unsigned long bist)
@@ -37,13 +41,11 @@ void stage1_main(unsigned long bist)
                "movl   %%esp, %0\n"
                : "=a" (v_esp)
        );
-       printk_spew("v_esp=%08x\n", v_esp);
+       printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
 #endif
 
-cpu_reset_x:
-
-        printk_spew("cpu_reset = %08x\n", cpu_reset);
-       printk_spew("No cache as ram now - ");
+        printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
+       printk(BIOS_SPEW, "No cache as ram now - ");
 
        /* store cpu_reset to ebx */
         __asm__ volatile (
@@ -83,5 +85,5 @@ cpu_reset_x:
        }
 
        /* We will not return */
-       printk_debug("sorry. parachute did not open.\n");
+       printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
 }