MTRR: get physical address size from CPUID

[coreboot.git] / src / cpu / intel / model_106cx / model_106cx_init.c

diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 2e38e775a6355a2c59d9aec915df07bd3ffea646..4bf2924fedf8c6b4407a3b799c3a4919440d7cef 100644 (file)
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -97,14 +97,16 @@ static void configure_c_states(void)
        // TODO Do we want Deep C4 and  Dynamic L2 shrinking?
        wrmsr(PMG_CST_CONFIG_CONTROL, msr);
 
-       // set P_BLK address
-       msr = rdmsr(PMG_IO_BASE_ADDR);
-       msr.lo = (PMB0 + 4) | (PMB1 << 16);
+       /* Set Processor MWAIT IO BASE (P_BLK) */
+       msr.hi = 0;
+       // TODO Do we want PM1_BASE? Needs SMM?
+       //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+       msr.lo = ((PMB0_BASE + 4) & 0xffff);
        wrmsr(PMG_IO_BASE_ADDR, msr);
 
-       // set C_LVL controls
-       msr = rdmsr(PMG_IO_CAPTURE_ADDR);
-       msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+       /* set C_LVL controls */
+       msr.hi = 0;
+       msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
        wrmsr(PMG_IO_CAPTURE_ADDR, msr);
 }
 
@@ -156,7 +158,7 @@ static void model_106cx_init(device_t cpu)
 #endif
 
        /* Setup MTRRs */
-       x86_setup_mtrrs(32);
+       x86_setup_mtrrs();
        x86_mtrr_check();
 
 #if CONFIG_USBDEBUG