/*
* This file is part of the coreboot project.
- *
+ *
* Copyright (C) 2007-2009 coresystems GmbH
*
* This program is free software; you can redistribute it and/or
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
-#include <cpu/x86/mtrr.h>
-#include <usbdebug_direct.h>
+#include <cpu/x86/name.h>
+#include <usbdebug.h>
static const uint32_t microcode_updates[] = {
+ #include "microcode-2963-M01106C2217.h"
+ #include "microcode-2964-M04106C2218.h"
+ #include "microcode-2965-M08106C2219.h"
+ #include "microcode-3098-M01106CA107.h"
+ #include "microcode-3101-M04106CA107.h"
+ #include "microcode-3104-M08106CA107.h"
+ #include "microcode-3107-M10106CA107.h"
+
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
0x0, 0x0, 0x0, 0x0,
};
-static inline void strcpy(char *dst, char *src)
-{
- while (*src) *dst++ = *src++;
-}
-
-static void fill_processor_name(char *processor_name)
-{
- struct cpuid_result regs;
- char temp_processor_name[49];
- char *processor_name_start;
- unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
- int i;
-
- for (i=0; i<3; i++) {
- regs = cpuid(0x80000002 + i);
- name_as_ints[i*4 + 0] = regs.eax;
- name_as_ints[i*4 + 1] = regs.ebx;
- name_as_ints[i*4 + 2] = regs.ecx;
- name_as_ints[i*4 + 3] = regs.edx;
- }
-
- temp_processor_name[48] = 0;
-
- /* Skip leading spaces */
- processor_name_start = temp_processor_name;
- while (*processor_name_start == ' ')
- processor_name_start++;
-
- memset(processor_name, 0, 49);
- strcpy(processor_name, processor_name_start);
-}
-
#define IA32_FEATURE_CONTROL 0x003a
#define CPUID_VMX (1 << 5)
#define PMG_CST_CONFIG_CONTROL 0xe2
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
-#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
-#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state.
- See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
+
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{
// TODO Do we want Deep C4 and Dynamic L2 shrinking?
wrmsr(PMG_CST_CONFIG_CONTROL, msr);
- // set P_BLK address
- msr = rdmsr(PMG_IO_BASE_ADDR);
- msr.lo = (PMB0 + 4) | (PMB1 << 16);
+ /* Set Processor MWAIT IO BASE (P_BLK) */
+ msr.hi = 0;
+ // TODO Do we want PM1_BASE? Needs SMM?
+ //msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+ msr.lo = ((PMB0_BASE + 4) & 0xffff);
wrmsr(PMG_IO_BASE_ADDR, msr);
- // set C_LVL controls
- msr = rdmsr(PMG_IO_CAPTURE_ADDR);
- msr.lo = (PMB0 + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
+ /* set C_LVL controls */
+ msr.hi = 0;
+ msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted
wrmsr(PMG_IO_CAPTURE_ADDR, msr);
}
wrmsr(IA32_MISC_ENABLE, msr);
}
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
static unsigned ehci_debug_addr;
#endif
/* Print processor name */
fill_processor_name(processor_name);
- printk_info("CPU: %s.\n", processor_name);
+ printk(BIOS_INFO, "CPU: %s.\n", processor_name);
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
// Is this caution really needed?
- if(!ehci_debug_addr)
+ if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif
/* Setup MTRRs */
- x86_setup_mtrrs(32);
+ x86_setup_mtrrs();
x86_mtrr_check();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif