Rename build system variables to be more intuitive, and

[coreboot.git] / src / cpu / intel / model_106cx / cache_as_ram.inc

diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index 873c6e94791ac57bbf43c4177d03767bcb2dd8bf..ab2469f11b0c29cc94e918b97d2e94a3323023cd 100644 (file)
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -23,7 +23,6 @@
 
 #include <cpu/x86/stack.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
 
        /* Save the BIST result */
        movl    %eax, %ebp
@@ -123,7 +122,7 @@ clear_mtrrs:
        movl    %eax, %cr0
 
        /* Set up stack pointer */
-#if defined(CONFIG_USBDEBUG_DIRECT) && (CONFIG_USBDEBUG_DIRECT == 1)
+#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
        /* leave some space for the struct ehci_debug_info */
        movl    $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
 #else
@@ -176,39 +175,12 @@ clear_mtrrs:
 
        post_code(0x33)
 
-#undef CLEAR_FIRST_1M_RAM
-#ifdef CLEAR_FIRST_1M_RAM
-       post_code(0x34)
-       /* Enable Write Combining and Speculative Reads for the first 1MB */
-       movl    $MTRRphysBase_MSR(0), %ecx
-       movl    $(0x00000000 | MTRR_TYPE_WRCOMB), %eax
-       xorl    %edx, %edx
-       wrmsr
-       movl    $MTRRphysMask_MSR(0), %ecx
-       movl    $(~(1024*1024 -1) | (1 << 11)), %eax
-       xorl    %edx, %edx
-       wrmsr
-       post_code(0x35)
-#endif
-
        /* Enable Cache */
        movl    %cr0, %eax
        andl    $~( (1 << 30) | (1 << 29) ), %eax
        movl    %eax, %cr0
 
-
        post_code(0x36)
-#ifdef CLEAR_FIRST_1M_RAM
-
-       /* Clear first 1MB of RAM */
-       movl    $0x00000000, %edi
-       cld
-       xorl    %eax, %eax
-       movl    $((1024*1024) / 4), %ecx
-       rep stosl
-
-       post_code(0x37)
-#endif
 
        /* Disable Cache */
        movl    %cr0, %eax