Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / cpu / amd / socket_S1G1 / Kconfig

diff --git a/src/cpu/amd/socket_S1G1/Kconfig b/src/cpu/amd/socket_S1G1/Kconfig
index 756a0499e2430770af7ec6a78fad230c65f465f0..284c1812c9da1d9f0b66abf1d6a44efa2d47e339 100644 (file)
--- a/src/cpu/amd/socket_S1G1/Kconfig
+++ b/src/cpu/amd/socket_S1G1/Kconfig
@@ -1,17 +1,38 @@
 config CPU_AMD_SOCKET_S1G1
         bool
+
+if CPU_AMD_SOCKET_S1G1
+
+config SOCKET_SPECIFIC_OPTIONS
+       def_bool y
        select K8_REV_F_SUPPORT
        select K8_HT_FREQ_1G_SUPPORT
        select CPU_AMD_MODEL_FXX
+       select CACHE_AS_RAM
 
 config CPU_SOCKET_TYPE
        hex
        default 0x12
-       depends on CPU_AMD_SOCKET_S1G1
 
 #DDR2 and REG, S1G1
 config DIMM_SUPPORT
        hex
        default 0x0204
-       depends on CPU_AMD_SOCKET_S1G1
 
+config CPU_ADDR_BITS
+       int
+       default 40
+
+config DCACHE_RAM_BASE
+       hex
+       default 0xc8000
+
+config DCACHE_RAM_SIZE
+       hex
+       default 0x08000
+
+config DCACHE_RAM_GLOBAL_VAR_SIZE
+       hex
+       default 0x01000
+
+endif