Move "select CACHE_AS_RAM" lines from boards into CPU socket.

[coreboot.git] / src / cpu / amd / socket_AM2r2 / Kconfig

diff --git a/src/cpu/amd/socket_AM2r2/Kconfig b/src/cpu/amd/socket_AM2r2/Kconfig
index e9989ef4ee9622ea0f80bf19f3224b559eee4ab6..c7cff14c04eb22f3626407c8a35ea9b73f84a676 100644 (file)
--- a/src/cpu/amd/socket_AM2r2/Kconfig
+++ b/src/cpu/amd/socket_AM2r2/Kconfig
@@ -2,15 +2,40 @@ config CPU_AMD_SOCKET_AM2R2
        bool
        select CPU_AMD_MODEL_10XXX
        select HT3_SUPPORT
+       select PCI_IO_CFG_EXT
+       select CACHE_AS_RAM
 
 config CPU_SOCKET_TYPE
        hex
        default 0x11
        depends on CPU_AMD_SOCKET_AM2R2
 
-# DDR2 and REG
-config DIMM_SUPPORT
+config EXT_RT_TBL_SUPPORT
+       bool
+       default n
+       depends on CPU_AMD_SOCKET_AM2R2
+
+config EXT_CONF_SUPPORT
+       bool
+       default n
+       depends on CPU_AMD_SOCKET_AM2R2
+
+config CBB
+       hex
+       default 0x0
+       depends on CPU_AMD_SOCKET_AM2R2
+
+config CDB
        hex
-       default 0x0104
+       default 0x18
        depends on CPU_AMD_SOCKET_AM2R2
 
+config XIP_ROM_BASE
+       hex
+       default 0xfff80000
+       depends on CPU_AMD_SOCKET_AM2R2
+
+config XIP_ROM_SIZE
+       hex
+       default 0x80000
+       depends on CPU_AMD_SOCKET_AM2R2