Fix Geode GX2 + LX caching for tiny bootblock.

[coreboot.git] / src / cpu / amd / model_lx / msrinit.c

diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 6569338a2f63ee7ff7885fdc5d975323e42c35ad..11182501c1c50c69627604a75a58154ec09d13cf 100644 (file)
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -22,10 +22,10 @@
 
 static const msrinit_t msr_table[] =
 {
-       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
+       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
                                                                   * Rom Properties: Write Serialize, WriteProtect.
                                                                   * RomBase: 0xFFFC0
-                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
+                                                                  * SysTop to RomBase Properties: Write Back.
                                                                   * SysTop: 0x000A0
                                                                   * System Memory Properties:  (Write Back) */
        {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
@@ -45,7 +45,7 @@ static const msrinit_t msr_table[] =
         * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
         * currently 1Mb.
         * These registers will be set to their correct value by the Northbridge init code.
-        * 
+        *
         * WARNING: if coreboot_ram could not be loaded, these registers are probably
         * incorrectly set here. You may comment the following two lines and set RAMBASE
         * to 0x4000 to revert to the previous behavior for LX-boards.