Fix Geode GX2 + LX caching for tiny bootblock.

[coreboot.git] / src / cpu / amd / model_lx / msrinit.c

diff --git a/src/cpu/amd/model_lx/msrinit.c b/src/cpu/amd/model_lx/msrinit.c
index 53c0a851dcba300224d371333c42803c8b1af030..11182501c1c50c69627604a75a58154ec09d13cf 100644 (file)
--- a/src/cpu/amd/model_lx/msrinit.c
+++ b/src/cpu/amd/model_lx/msrinit.c
@@ -18,18 +18,14 @@
  */
 
 #include <stdlib.h>
+#include "cpu/x86/msr.h"
 
-struct msrinit {
-       u32 msrnum;
-       msr_t msr;
-};
-
-static const struct msrinit msr_table[] =
+static const msrinit_t msr_table[] =
 {
-       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, /* Setup access to cache under 1MB.
+       {CPU_RCONF_DEFAULT, {.hi = 0x24fffc00,.lo = 0x0000A000}}, /* Setup access to cache under 1MB.
                                                                   * Rom Properties: Write Serialize, WriteProtect.
                                                                   * RomBase: 0xFFFC0
-                                                                  * SysTop to RomBase Properties: Write Serialize, Cache Disable.
+                                                                  * SysTop to RomBase Properties: Write Back.
                                                                   * SysTop: 0x000A0
                                                                   * System Memory Properties:  (Write Back) */
        {CPU_RCONF_A0_BF,   {.hi = 0x00000000,.lo = 0x00000000}}, /* 0xA0000-0xBFFFF : (Write Back) */
@@ -43,13 +39,26 @@ static const struct msrinit msr_table[] =
        {MSR_GLIU1_BASE1,   {.hi = 0x20000000,.lo = 0x000fff80}}, // 0x00000-0x7FFFF
        {MSR_GLIU1_BASE2,   {.hi = 0x20000000,.lo = 0x080fffe0}}, // 0x80000-0x9FFFF
        {MSR_GLIU1_SHADOW,  {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF
+
+       /* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
+        * It doesn't really matter in fact how much, however, because the only usage
+        * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
+        * currently 1Mb.
+        * These registers will be set to their correct value by the Northbridge init code.
+        *
+        * WARNING: if coreboot_ram could not be loaded, these registers are probably
+        * incorrectly set here. You may comment the following two lines and set RAMBASE
+        * to 0x4000 to revert to the previous behavior for LX-boards.
+        */
+       {MSR_GLIU0_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
+       {MSR_GLIU1_SYSMEM,  {.hi = 0x2000001F,.lo = 0x6BF00100}}, // 0x100000-0x1F6BF000
 };
 
 static void msr_init(void)
 {
        int i;
        for (i = 0; i < ARRAY_SIZE(msr_table); i++)
-               wrmsr(msr_table[i].msrnum, msr_table[i].msr);
+               wrmsr(msr_table[i].index, msr_table[i].msr);
 }