Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / cpu / amd / model_lx / cpubug.c

diff --git a/src/cpu/amd/model_lx/cpubug.c b/src/cpu/amd/model_lx/cpubug.c
index ce81929b1801cf46e23be9d23fc5de0ac8df3e78..e3b6e511eef417090329f114ef41d0df2072d119 100644 (file)
--- a/src/cpu/amd/model_lx/cpubug.c
+++ b/src/cpu/amd/model_lx/cpubug.c
@@ -1,5 +1,5 @@
 /*
- * This file is part of the LinuxBIOS project.
+ * This file is part of the coreboot project.
  *
  * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa@artecdesign.ee>
  * Copyright (C) 2006 Ronald G. Minnich <rminnich@gmail.com>
@@ -30,7 +30,6 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/lxdef.h>
 
-
 /**************************************************************************
  *
  *     pcideadlock
@@ -40,27 +39,27 @@
  *     There is also fix code in cache and PCI functions. This bug is very is pervasive.
  *
  **************************************************************************/
-static void pcideadlock(void){
+static void pcideadlock(void)
+{
        msr_t msr;
 
        /*
-        * forces serialization of all load misses. Setting this bit prevents the 
-        * DM pipe from backing up if a read request has to be held up waiting 
+        * forces serialization of all load misses. Setting this bit prevents the
+        * DM pipe from backing up if a read request has to be held up waiting
         * for PCI writes to complete.
-       */
+        */
        msr = rdmsr(CPU_DM_CONFIG0);
        msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
        wrmsr(CPU_DM_CONFIG0, msr);
 
-       
-       /* write serialize memory hole to PCI. Need to unWS when something is 
+       /* write serialize memory hole to PCI. Need to unWS when something is
         * shadowed regardless of cachablility.
         */
        msr.lo = 0x021212121;
        msr.hi = 0x021212121;
-       wrmsr( CPU_RCONF_A0_BF, msr);
-       wrmsr( CPU_RCONF_C0_DF, msr);
-       wrmsr( CPU_RCONF_E0_FF, msr);
+       wrmsr(CPU_RCONF_A0_BF, msr);
+       wrmsr(CPU_RCONF_C0_DF, msr);
+       wrmsr(CPU_RCONF_E0_FF, msr);
 }
 
 /****************************************************************************/
@@ -74,17 +73,19 @@ static void pcideadlock(void){
 /**     to maintain coherency with and the cache is not enabled yet.*/
 /***/
 /****************************************************************************/
-static void disablememoryreadorder(void){
+static void disablememoryreadorder(void)
+{
        msr_t msr;
 
        msr = rdmsr(MC_CF8F_DATA);
-       msr.hi |=  CF8F_UPPER_REORDER_DIS_SET;
+       msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
        wrmsr(MC_CF8F_DATA, msr);
 }
 
 /* For cpu version C3. Should be the only released version */
-void cpubug(void) {
-                       pcideadlock();
+void cpubug(void)
+{
+       pcideadlock();
        disablememoryreadorder();
-       printk_debug("Done cpubug fixes \n");
+       printk(BIOS_DEBUG, "Done cpubug fixes \n");
 }