printk_foo -> printk(BIOS_FOO, ...)

[coreboot.git] / src / cpu / amd / model_fxx / powernow_acpi.c

diff --git a/src/cpu/amd/model_fxx/powernow_acpi.c b/src/cpu/amd/model_fxx/powernow_acpi.c
index 1e789e3729a0c9cbe0fd1c2c27c1437d38d431ef..5339f3b5bffe2250d3a81d6e47bc76c9a63dd05d 100644 (file)
--- a/src/cpu/amd/model_fxx/powernow_acpi.c
+++ b/src/cpu/amd/model_fxx/powernow_acpi.c
@@ -5,8 +5,8 @@
  * Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License v2 as published by
- * the Free Software Foundation.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -32,7 +32,8 @@
 
 static int write_pstates_for_core(u8 pstate_num, u16 *pstate_feq, u8 *pstate_vid,
                                u8 *pstate_fid, u32 *pstate_power, int coreID,
-                               u32 pcontrol_blk, u8 plen, u8 onlyBSP)  {
+                               u32 pcontrol_blk, u8 plen, u8 onlyBSP)
+{
        int lenp, lenpr, i;
 
        if ((onlyBSP) && (coreID != 0)) {
@@ -155,21 +156,21 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
        v[10] = cpuid1.ecx;
        v[11] = cpuid1.edx;
        processor_brand[48] = 0;
-       printk_info("processor_brand=%s\n", processor_brand);
+       printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
 
        /*
         * Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
         * socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
         * cmp_cap : 0x0 SingleCore ; 0x1 DualCore
         */
-       printk_info("Pstates Algorithm ...\n");
+       printk(BIOS_INFO, "Pstates Algorithm ...\n");
        cmp_cap =
            (pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
             0x3000) >> 12;
        cpuid1 = cpuid(0x80000001);
        pwr_lmt = ((cpuid1.ebx & 0x1C0) >> 5) | ((cpuid1.ebx & 0x4000) >> 14);
        for (index = 0; index <= sizeof(TDP) / sizeof(TDP[0]); index++)
-               if (TDP[index].socket_type == CPU_SOCKET_TYPE &&
+               if (TDP[index].socket_type == CONFIG_CPU_SOCKET_TYPE &&
                    TDP[index].cmp_cap == cmp_cap &&
                    TDP[index].pwr_lmt == pwr_lmt) {
                        power_limit = TDP[index].power_limit;
@@ -180,7 +181,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
        /* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
        cpuid1 = cpuid(0x80000007);
        if ((cpuid1.edx & 0x6) != 0x6) {
-               printk_info("No valid set of P-states\n");
+               printk(BIOS_INFO, "No valid set of P-states\n");
                goto write_pstates;
        }
 
@@ -203,7 +204,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
                PstateStep_coef = 2;
 
        if (IntPstateSup == 0) {
-               printk_info("No intermediate P-states are supported\n");
+               printk(BIOS_INFO, "No intermediate P-states are supported\n");
                goto write_pstates;
        }
 
@@ -351,12 +352,12 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
        /* Print Pstate freq,vid,volt,power */
 
        for (index = 0; index < Pstate_num; index++) {
-               printk_info("Pstate_freq[%d] = %dMHz\t", index,
+               printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
                            Pstate_feq[index]);
-               printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
-               printk_info("Pstate_volt[%d] = %dmv\t", index,
+               printk(BIOS_INFO, "Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
+               printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index,
                            Pstate_volt[index]);
-               printk_info("Pstate_power[%d] = %dmw\n", index,
+               printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
                            Pstate_power[index]);
        }
 
@@ -374,9 +375,10 @@ write_pstates:
        return len;
 }
 
-int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP) {
+int amd_model_fxx_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
+{
        int lens;
-       char pscope[] = "\\_PR_";
+       char pscope[] = "\\_PR";
 
        lens = acpigen_write_scope(pscope);
        lens += pstates_algorithm(pcontrol_blk, plen, onlyBSP);