* Copyright 2005 AMD
* 2005.08 yhlu add microcode support
-*/
+ */
+
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
-
-#include "../../../northbridge/amd/amdk8/amdk8.h"
-
+#include "northbridge/amd/amdk8/amdk8.h"
#include <cpu/amd/model_fxx_rev.h>
#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
-
#include <cpu/amd/multicore.h>
-
#include <cpu/amd/model_fxx_msr.h>
#if CONFIG_WAIT_BEFORE_CPUS_INIT
msr_t base;
msr_t mask;
};
+
struct mtrr_state {
struct mtrr mtrrs[MTRR_COUNT];
msr_t top_mem, top_mem2;
}
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
static unsigned ehci_debug_addr;
#endif
unsigned long i;
msr_t msr;
struct node_core_id id;
-#if CONFIG_LOGICAL_CPUS == 1
- u32 siblings;
-#endif
-#if CONFIG_K8_REV_F_SUPPORT == 1
- struct cpuinfo_x86 c;
-
- get_fms(&c, dev->device);
-#endif
-
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
if (!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
amd_setup_mtrrs();
x86_mtrr_check();
-#if CONFIG_USBDEBUG_DIRECT
+#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif
setup_lapic();
#if CONFIG_LOGICAL_CPUS == 1
- siblings = cpuid_ecx(0x80000008) & 0xff;
+ u32 siblings = cpuid_ecx(0x80000008) & 0xff;
if (siblings > 0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
*/
if (id.coreid == 0)
init_ecc_memory(id.nodeid); // only do it for core 0
-
-#if CONFIG_LOGICAL_CPUS==1
- /* Start up my cpu siblings */
-// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
-#endif
-
}
static struct device_operations cpu_dev_ops = {