* 2004.11 yhlu add d0 e0 support
* 2004.12 yhlu add dual core support
* 2005.02 yhlu add e0 memory hole support
+
+ * Copyright 2005 AMD
+ * 2005.08 yhlu add microcode support
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
-#include <device/device.h>
#include <device/pci.h>
#include <string.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
+
#include "../../../northbridge/amd/amdk8/amdk8.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
+
+#include <cpu/amd/model_fxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/mem.h>
-#if CONFIG_LOGICAL_CPUS==1
#include <cpu/amd/dualcore.h>
+
+#include <cpu/amd/model_fxx_msr.h>
+
+void cpus_ready_for_init(void)
+{
+#if CONFIG_MEM_TRAIN_SEQ == 1
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ // wait for ap memory to trained
+ wait_all_core0_mem_trained(sysinfox);
#endif
+}
+
-#include "model_fxx_msr.h"
+#if CONFIG_K8_REV_F_SUPPORT == 0
+int is_e0_later_in_bsp(int nodeid)
+{
+ uint32_t val;
+ uint32_t val_old;
+ int e0_later;
+ if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
+ return !is_cpu_pre_e0();
+ }
+ // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
+ if(!dev) return 0;
+ val_old = pci_read_config32(dev, 0x80);
+ val = val_old;
+ val |= (1<<3);
+ pci_write_config32(dev, 0x80, val);
+ val = pci_read_config32(dev, 0x80);
+ e0_later = !!(val & (1<<3));
+ if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
+ pci_write_config32(dev, 0x80, val_old); // restore it
+ }
+
+ return e0_later;
+}
+#endif
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+int is_cpu_f0_in_bsp(int nodeid)
+{
+ uint32_t dword;
+ device_t dev;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
+ dword = pci_read_config32(dev, 0xfc);
+ return (dword & 0xfff00) == 0x40f00;
+}
+#endif
#define MCI_STATUS 0x401
}
-
#define MTRR_COUNT 8
#define ZERO_CHUNK_KB 0x800UL /* 2M */
#define TOLM_KB 0x400000UL
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRRphysBase_MSR(0), msr);
msr.hi = 0x000000ff;
- msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
+ msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
wrmsr(MTRRphysMask_MSR(0), msr);
/* Set the default type to write combining */
enable_cache();
}
+static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
+{
+ unsigned long limitk;
+ unsigned long size;
+ void *addr;
+
+ /* Report every 64M */
+ if ((basek % (64*1024)) == 0) {
+
+ /* Restore the normal state */
+ map_2M_page(0);
+ restore_mtrr_state(mtrr_state);
+ enable_lapic();
+
+ /* Print a status message */
+ printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
+
+ /* Return to the initialization state */
+ set_init_ecc_mtrrs();
+ disable_lapic();
+
+ }
+
+ limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
+#if 0
+ /* couldn't happen, memory must on 2M boundary */
+ if(limitk>endk) {
+ limitk = enk;
+ }
+#endif
+ size = (limitk - basek) << 10;
+ addr = map_2M_page(basek >> 11);
+ if (addr == MAPPING_ERROR) {
+ printk_err("Cannot map page: %lx\n", basek >> 11);
+ return;
+ }
+
+ /* clear memory 2M (limitk - basek) */
+ addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
+ clear_memory(addr, size);
+}
+
static void init_ecc_memory(unsigned node_id)
{
unsigned long startk, begink, endk;
-#if K8_E0_MEM_HOLE_SIZEK != 0
- unsigned long hole_startk = 0, hole_endk = 0;
-#endif
+ unsigned long hole_startk = 0;
unsigned long basek;
struct mtrr_state mtrr_state;
+
device_t f1_dev, f2_dev, f3_dev;
int enable_scrubbing;
uint32_t dcl;
/* If ecc support is not enabled don't touch memory */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl & DCL_DimmEccEn)) {
+ printk_debug("ECC Disabled\n");
return;
}
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
-#if K8_E0_MEM_HOLE_SIZEK != 0
- if (!is_cpu_pre_e0()) {
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ #if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_e0())
+ {
+ #endif
+
uint32_t val;
val = pci_read_config32(f1_dev, 0xf0);
- if((val & 1)==1) {
+ if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10);
- hole_endk = ((val & (0xff<<8))<<(16-10)) - startk;
- hole_endk += hole_startk;
}
+ #if CONFIG_K8_REV_F_SUPPORT == 0
}
+ #endif
#endif
/* Don't start too early */
begink = startk;
- if (begink < CONFIG_LB_MEM_TOPK) {
- begink = CONFIG_LB_MEM_TOPK;
+ if (begink < (CONFIG_RAMTOP >> 10)) {
+ begink = (CONFIG_RAMTOP >>10);
}
- printk_debug("Clearing memory %uK - %uK: ", startk, endk);
+
+ printk_debug("Clearing memory %luK - %luK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
disable_lapic();
/* Walk through 2M chunks and zero them */
- for(basek = begink; basek < endk; basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1))) {
- unsigned long limitk;
- unsigned long size;
- void *addr;
-
-#if K8_E0_MEM_HOLE_SIZEK != 0
- if ((basek >= hole_startk) && (basek < hole_endk)) continue;
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ /* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
+ if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
+ for(basek = begink; basek < hole_startk;
+ basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
+ {
+ clear_2M_ram(basek, &mtrr_state);
+ }
+ for(basek = 4*1024*1024; basek < endk;
+ basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
+ {
+ clear_2M_ram(basek, &mtrr_state);
+ }
+ }
+ else
#endif
- /* Report every 64M */
- if ((basek % (64*1024)) == 0) {
- /* Restore the normal state */
- map_2M_page(0);
- restore_mtrr_state(&mtrr_state);
- enable_lapic();
-
- /* Print a status message */
- printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
-
- /* Return to the initialization state */
- set_init_ecc_mtrrs();
- disable_lapic();
- }
+ for(basek = begink; basek < endk;
+ basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
+ {
+ clear_2M_ram(basek, &mtrr_state);
+ }
- limitk = (basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1);
- if (limitk > endk) {
- limitk = endk;
- }
- size = (limitk - basek) << 10;
- addr = map_2M_page(basek >> 11);
- addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
- if (addr == MAPPING_ERROR) {
- continue;
- }
- /* clear memory 2M (limitk - basek) */
- clear_memory(addr, size);
- }
/* Restore the normal state */
map_2M_page(0);
restore_mtrr_state(&mtrr_state);
printk_debug(" done\n");
}
+
static inline void k8_errata(void)
{
msr_t msr;
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
* FIXME this is only needed if ECC is enabled.
*/
msr.hi |= 1 << (36 - 32);
- }
+ }
wrmsr(NB_CFG_MSR, msr);
}
-// AMD_D0_SUPPORT
+
+ /* Erratum 97 ... */
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
- /* D0 later don't need it */
- /* Erratum 97 ... */
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= 1 << 3;
wrmsr_amd(DC_CFG_MSR, msr);
- }
-
-//AMD_D0_SUPPORT
- if(is_cpu_pre_d0()) {
- /*D0 later don't need it */
- /* Erratum 94 ... */
+ }
+
+ /* Erratum 94 ... */
+ if (is_cpu_pre_d0()) {
msr = rdmsr_amd(IC_CFG_MSR);
msr.lo |= 1 << 11;
wrmsr_amd(IC_CFG_MSR, msr);
/* Erratum 91 prefetch miss is handled in the kernel */
-//AMD_D0_SUPPORT
+ /* Erratum 106 ... */
+ msr = rdmsr_amd(LS_CFG_MSR);
+ msr.lo |= 1 << 25;
+ wrmsr_amd(LS_CFG_MSR, msr);
+
+ /* Erratum 107 ... */
+ msr = rdmsr_amd(BU_CFG_MSR);
+ msr.hi |= 1 << (43 - 32);
+ wrmsr_amd(BU_CFG_MSR, msr);
+
if(is_cpu_d0()) {
/* Erratum 110 ...*/
msr = rdmsr_amd(CPU_ID_HYPER_EXT_FEATURES);
msr.hi |=1;
wrmsr_amd(CPU_ID_HYPER_EXT_FEATURES, msr);
- }
+ }
+#endif
-//AMD_E0_SUPPORT
- if(!is_cpu_pre_e0()) {
- /* Erratum 110 ...*/
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_e0())
+#endif
+ {
+ /* Erratum 110 ... */
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
msr.hi |=1;
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
+
+ /* Erratum 122 */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= 1 << 6;
+ wrmsr(HWCR_MSR, msr);
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+ /* Erratum 131... */
+ msr = rdmsr(NB_CFG_MSR);
+ msr.lo |= 1 << 20;
+ wrmsr(NB_CFG_MSR, msr);
+#endif
+
}
+extern void model_fxx_update_microcode(unsigned cpu_deviceid);
+int init_processor_name(void);
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+
void model_fxx_init(device_t dev)
{
unsigned long i;
msr_t msr;
-#if CONFIG_LOGICAL_CPUS==1
struct node_core_id id;
- unsigned siblings;
- id.coreid=0;
-#else
- unsigned nodeid;
+#if CONFIG_LOGICAL_CPUS == 1
+ unsigned siblings;
+#endif
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+ struct cpuinfo_x86 c;
+
+ get_fms(&c, dev->device);
+#endif
+
+#if CONFIG_USBDEBUG_DIRECT
+ if(!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
#endif
/* Turn on caching if we haven't already */
- x86_enable_cache();
+ x86_enable_cache();
amd_setup_mtrrs();
x86_mtrr_check();
+#if CONFIG_USBDEBUG_DIRECT
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Update the microcode */
+ model_fxx_update_microcode(dev->device);
+
disable_cache();
/* zero the machine check error status registers */
k8_errata();
+ /* Set SMMLOCK to avoid exploits messing with SMM */
+ msr = rdmsr(HWCR_MSR);
+ msr.lo |= (1 << 0);
+ wrmsr(HWCR_MSR, msr);
+
+ /* Set the processor name string */
+ init_processor_name();
+
enable_cache();
-#if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
- siblings = cpuid_ecx(0x80000008) & 0xff;
+ /* Enable the local cpu apics */
+ setup_lapic();
-// id = get_node_core_id((!is_cpu_pre_e0())? read_nb_cfg_54():0);
- id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
+#if CONFIG_LOGICAL_CPUS == 1
+ siblings = cpuid_ecx(0x80000008) & 0xff;
if(siblings>0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
msr.hi |= 1<<(33-32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
-
+
+#endif
+
+ id = get_node_core_id(read_nb_cfg_54()); // pre e0 nb_cfg_54 can not be set
+
/* Is this a bad location? In particular can another node prefecth
* data from this node before we have initialized it?
*/
- if(id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core0
-#else
- /* For now there is a 1-1 mapping between node_id and cpu_id */
- nodeid = lapicid() & 0x7;
- init_ecc_memory(nodeid);
-#endif
-
- /* Enable the local cpu apics */
- setup_lapic();
+ if (id.coreid == 0) init_ecc_memory(id.nodeid); // only do it for core 0
#if CONFIG_LOGICAL_CPUS==1
-//AMD_DUAL_CORE_SUPPORT
/* Start up my cpu siblings */
// if(id.coreid==0) amd_sibling_init(dev); // Don't need core1 is already be put in the CPU BUS in bus_cpu_scan
#endif
+
}
static struct device_operations cpu_dev_ops = {
.init = model_fxx_init,
};
+
static struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_AMD, 0xf50 }, /* B3 */
- { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
- { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
- { X86_VENDOR_AMD, 0xf48 },
-#if 1
- { X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
- { X86_VENDOR_AMD, 0xf4A },
- { X86_VENDOR_AMD, 0xf7A },
- { X86_VENDOR_AMD, 0xfc0 }, /* DH7-CG */
- { X86_VENDOR_AMD, 0xfe0 },
- { X86_VENDOR_AMD, 0xff0 },
- { X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
- { X86_VENDOR_AMD, 0xfb2 },
-//AMD_D0_SUPPORT
- { X86_VENDOR_AMD, 0x10f50 }, /* SH7-D0 */
- { X86_VENDOR_AMD, 0x10f40 },
- { X86_VENDOR_AMD, 0x10f70 },
- { X86_VENDOR_AMD, 0x10fc0 }, /* DH7-D0 */
- { X86_VENDOR_AMD, 0x10ff0 },
- { X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
- { X86_VENDOR_AMD, 0x10fb0 },
-//AMD_E0_SUPPORT
- { X86_VENDOR_AMD, 0x20f50 }, /* SH7-E0*/
- { X86_VENDOR_AMD, 0x20f40 },
- { X86_VENDOR_AMD, 0x20f70 },
- { X86_VENDOR_AMD, 0x20fc0 }, /* DH7-E0 */ /* DH-E3 */
- { X86_VENDOR_AMD, 0x20ff0 },
- { X86_VENDOR_AMD, 0x20f10 }, /* JH7-E0 */
- { X86_VENDOR_AMD, 0x20f30 },
- { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
- { X86_VENDOR_AMD, 0x20f71 },
- { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 */
- { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 */
- { X86_VENDOR_AMD, 0x20fc2 },
- { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
- { X86_VENDOR_AMD, 0x20f32 },
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
+ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
+ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
+ { X86_VENDOR_AMD, 0xf58 }, /* SH-C0 (socket 940) */
+ { X86_VENDOR_AMD, 0xf48 }, /* SH-C0 (socket 754) */
+ { X86_VENDOR_AMD, 0xf5a }, /* SH-CG (socket 940) */
+ { X86_VENDOR_AMD, 0xf4a }, /* SH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xf7a }, /* SH-CG (socket 939) */
+ { X86_VENDOR_AMD, 0xfc0 }, /* DH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xfe0 }, /* DH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xff0 }, /* DH-CG (socket 939) */
+ { X86_VENDOR_AMD, 0xf82 }, /* CH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xfb2 }, /* CH-CG (socket 939) */
+
+ /* AMD D0 support */
+ { X86_VENDOR_AMD, 0x10f50 }, /* SH-D0 (socket 940) */
+ { X86_VENDOR_AMD, 0x10f40 }, /* SH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10f70 }, /* SH-D0 (socket 939) */
+ { X86_VENDOR_AMD, 0x10fc0 }, /* DH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10ff0 }, /* DH-D0 (socket 939) */
+ { X86_VENDOR_AMD, 0x10f80 }, /* CH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10fb0 }, /* CH-D0 (socket 939) */
+
+ /* AMD E0 support */
+ { X86_VENDOR_AMD, 0x20f50 }, /* SH-E0 */
+ { X86_VENDOR_AMD, 0x20f40 },
+ { X86_VENDOR_AMD, 0x20f70 },
+ { X86_VENDOR_AMD, 0x20fc0 }, /* DH-E3 (socket 754) */
+ { X86_VENDOR_AMD, 0x20ff0 }, /* DH-E3 (socket 939) */
+ { X86_VENDOR_AMD, 0x20f10 }, /* JH-E1 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f71 }, /* SH-E4 (socket 939) */
+ { X86_VENDOR_AMD, 0x20fb1 }, /* BH-E4 (socket 939) */
+ { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 (socket 754) */
+ { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 (socket 939) */
+ { X86_VENDOR_AMD, 0x20fc2 }, /* DH-E6 (socket 754) */
+ { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f32 }, /* JH-E6 (socket 939) */
+ { X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
+#endif
+
+#if CONFIG_K8_REV_F_SUPPORT == 1
+ /*
+ * AMD F0 support.
+ *
+ * See Revision Guide for AMD NPT Family 0Fh Processors,
+ * Publication #33610, Revision: 3.30, February 2008.
+ *
+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
+ */
+ { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f70 }, /* SH-F0 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f40 }, /* SH-F0 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f31 }, /* JH-F1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f01 }, /* JH-F1 (socket S1g1) */
+
+ { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f32 }, /* JH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f82 }, /* BH-F2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */
+ { X86_VENDOR_AMD, 0x50fd3 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60f81 }, /* BH-G1 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x60fb2 }, /* BH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60f82 }, /* BH-G2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x70ff1 }, /* DH-G1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60ff2 }, /* DH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x70ff2 }, /* DH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60fc2 }, /* DH-G2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x70fc2 }, /* DH-G2 (socket S1g1) */
#endif
{ 0, 0 },
};
-static struct cpu_driver model_fxx __cpu_driver = {
+
+static const struct cpu_driver model_fxx __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};
projects / coreboot.git / blobdiff