* 2005.02 yhlu add e0 memory hole support
* Copyright 2005 AMD
- * 2005.08 yhlu add microcode support
+ * 2005.08 yhlu add microcode support
*/
#include <console/console.h>
#include <cpu/x86/msr.h>
#include "../../../northbridge/amd/amdk8/amdk8.h"
#include <cpu/amd/model_fxx_rev.h>
+#include <cpu/amd/microcode.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
#include <cpu/amd/dualcore.h>
#include <cpu/amd/model_fxx_msr.h>
+#if CONFIG_WAIT_BEFORE_CPUS_INIT
void cpus_ready_for_init(void)
{
-#if MEM_TRAIN_SEQ == 1
- struct sys_info *sysinfox = (struct sys_info *)((CONFIG_LB_MEM_TOPK<<10) - DCACHE_RAM_GLOBAL_VAR_SIZE);
+#if CONFIG_MEM_TRAIN_SEQ == 1
+ struct sys_info *sysinfox = (struct sys_info *)((CONFIG_RAMTOP) - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
// wait for ap memory to trained
wait_all_core0_mem_trained(sysinfox);
#endif
}
+#endif
-
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
}
#endif
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
{
int i;
for(i = 0; i < MTRR_COUNT; i++) {
- printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
+ printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n",
i,
state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
}
- printk_debug("top_mem: %08x%08x\n",
+ printk(BIOS_DEBUG, "top_mem: %08x%08x\n",
state->top_mem.hi, state->top_mem.lo);
- printk_debug("top_mem2: %08x%08x\n",
+ printk(BIOS_DEBUG, "top_mem2: %08x%08x\n",
state->top_mem2.hi, state->top_mem2.lo);
- printk_debug("def_type: %08x%08x\n",
+ printk(BIOS_DEBUG, "def_type: %08x%08x\n",
state->def_type.hi, state->def_type.lo);
}
#endif
msr.lo = 0x00000000 | MTRR_TYPE_WRBACK;
wrmsr(MTRRphysBase_MSR(0), msr);
msr.hi = 0x000000ff;
- msr.lo = ~((CONFIG_LB_MEM_TOPK << 10) - 1) | 0x800;
+ msr.lo = ~((CONFIG_RAMTOP) - 1) | 0x800;
wrmsr(MTRRphysMask_MSR(0), msr);
/* Set the default type to write combining */
enable_cache();
}
-static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
+static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_state)
{
unsigned long limitk;
unsigned long size;
enable_lapic();
/* Print a status message */
- printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
+ printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB)?'+':'-');
/* Return to the initialization state */
set_init_ecc_mtrrs();
#if 0
/* couldn't happen, memory must on 2M boundary */
if(limitk>endk) {
- limitk = enk;
+ limitk = enk;
}
#endif
size = (limitk - basek) << 10;
addr = map_2M_page(basek >> 11);
if (addr == MAPPING_ERROR) {
- printk_err("Cannot map page: %x\n", basek >> 11);
+ printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11);
return;
}
/* clear memory 2M (limitk - basek) */
addr = (void *)(((uint32_t)addr) | ((basek & 0x7ff) << 10));
- clear_memory(addr, size);
+ memset(addr, 0, size);
}
static void init_ecc_memory(unsigned node_id)
} else {
pci_write_config32(f3_dev, SCRUB_CONTROL,
(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
- printk_debug("Scrubbing Disabled\n");
+ printk(BIOS_DEBUG, "Scrubbing Disabled\n");
}
-
+
/* If ecc support is not enabled don't touch memory */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl & DCL_DimmEccEn)) {
- printk_debug("ECC Disabled\n");
+ printk(BIOS_DEBUG, "ECC Disabled\n");
return;
}
startk = (pci_read_config32(f1_dev, 0x40 + (node_id*8)) & 0xffff0000) >> 2;
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
-#if HW_MEM_HOLE_SIZEK != 0
- #if K8_REV_F_SUPPORT == 0
- if (!is_cpu_pre_e0())
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
+ #if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_e0())
{
#endif
if(val & 1) {
hole_startk = ((val & (0xff<<24)) >> 10);
}
- #if K8_REV_F_SUPPORT == 0
+ #if CONFIG_K8_REV_F_SUPPORT == 0
}
#endif
#endif
-
+
/* Don't start too early */
begink = startk;
- if (begink < CONFIG_LB_MEM_TOPK) {
- begink = CONFIG_LB_MEM_TOPK;
+ if (begink < (CONFIG_RAMTOP >> 10)) {
+ begink = (CONFIG_RAMTOP >>10);
}
- printk_debug("Clearing memory %uK - %uK: ", begink, endk);
+ printk(BIOS_DEBUG, "Clearing memory %luK - %luK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
disable_lapic();
/* Walk through 2M chunks and zero them */
-#if HW_MEM_HOLE_SIZEK != 0
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* here hole_startk can not be equal to begink, never. Also hole_startk is in 2M boundary, 64M? */
if ( (hole_startk != 0) && ((begink < hole_startk) && (endk>(4*1024*1024)))) {
for(basek = begink; basek < hole_startk;
clear_2M_ram(basek, &mtrr_state);
}
}
- else
+ else
#endif
for(basek = begink; basek < endk;
- basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
+ basek = ((basek + ZERO_CHUNK_KB) & ~(ZERO_CHUNK_KB - 1)))
{
clear_2M_ram(basek, &mtrr_state);
}
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
}
- printk_debug(" done\n");
+ printk(BIOS_DEBUG, " done\n");
}
static inline void k8_errata(void)
{
msr_t msr;
-#if K8_REV_F_SUPPORT == 0
+#if CONFIG_K8_REV_F_SUPPORT == 0
if (is_cpu_pre_c0()) {
/* Erratum 63... */
msr = rdmsr(HWCR_MSR);
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= (1 << 10);
wrmsr_amd(DC_CFG_MSR, msr);
-
+
}
/* I can't touch this msr on early buggy cpus */
if (!is_cpu_pre_b3()) {
/* Erratum 89 ... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 3;
-
+
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
/* D0 later don't need it */
- /* Erratum 86 Disable data masking on C0 and
+ /* Erratum 86 Disable data masking on C0 and
* later processor revs.
* FIXME this is only needed if ECC is enabled.
*/
}
wrmsr(NB_CFG_MSR, msr);
}
-
+
/* Erratum 97 ... */
if (!is_cpu_pre_c0() && is_cpu_pre_d0()) {
msr = rdmsr_amd(DC_CFG_MSR);
msr.lo |= 1 << 3;
wrmsr_amd(DC_CFG_MSR, msr);
- }
-
+ }
+
/* Erratum 94 ... */
if (is_cpu_pre_d0()) {
msr = rdmsr_amd(IC_CFG_MSR);
}
#endif
-#if K8_REV_F_SUPPORT == 0
- if (!is_cpu_pre_e0())
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ if (!is_cpu_pre_e0())
#endif
{
/* Erratum 110 ... */
msr.lo |= 1 << 6;
wrmsr(HWCR_MSR, msr);
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
/* Erratum 131... */
msr = rdmsr(NB_CFG_MSR);
msr.lo |= 1 << 20;
}
-extern void model_fxx_update_microcode(unsigned cpu_deviceid);
-int init_processor_name(void);
-
+#if CONFIG_USBDEBUG_DIRECT
static unsigned ehci_debug_addr;
+#endif
-void model_fxx_init(device_t dev)
+static void model_fxx_init(device_t dev)
{
unsigned long i;
msr_t msr;
unsigned siblings;
#endif
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
struct cpuinfo_x86 c;
-
+
get_fms(&c, dev->device);
#endif
#if CONFIG_USBDEBUG_DIRECT
- if(!ehci_debug_addr)
+ if(!ehci_debug_addr)
ehci_debug_addr = get_ehci_debug();
set_ehci_debug(0);
#endif
model_fxx_update_microcode(dev->device);
disable_cache();
-
+
/* zero the machine check error status registers */
msr.lo = 0;
msr.hi = 0;
}
k8_errata();
-
+
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
wrmsr(HWCR_MSR, msr);
-
+
/* Set the processor name string */
init_processor_name();
-
+
enable_cache();
/* Enable the local cpu apics */
if(siblings>0) {
msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
- msr.lo |= 1 << 28;
+ msr.lo |= 1 << 28;
wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
msr = rdmsr_amd(LOGICAL_CPUS_NUM_MSR);
- msr.lo = (siblings+1)<<16;
+ msr.lo = (siblings+1)<<16;
wrmsr_amd(LOGICAL_CPUS_NUM_MSR, msr);
msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
- msr.hi |= 1<<(33-32);
+ msr.hi |= 1<<(33-32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
- }
+ }
#endif
static struct device_operations cpu_dev_ops = {
.init = model_fxx_init,
};
+
static struct cpu_device_id cpu_table[] = {
-#if K8_REV_F_SUPPORT == 0
- { X86_VENDOR_AMD, 0xf50 }, /* B3 */
- { X86_VENDOR_AMD, 0xf51 }, /* SH7-B3 */
- { X86_VENDOR_AMD, 0xf58 }, /* SH7-C0 */
- { X86_VENDOR_AMD, 0xf48 },
-
- { X86_VENDOR_AMD, 0xf5A }, /* SH7-CG */
- { X86_VENDOR_AMD, 0xf4A },
- { X86_VENDOR_AMD, 0xf7A },
- { X86_VENDOR_AMD, 0xfc0 }, /* DH7-CG */
- { X86_VENDOR_AMD, 0xfe0 },
- { X86_VENDOR_AMD, 0xff0 },
- { X86_VENDOR_AMD, 0xf82 }, /* CH7-CG */
- { X86_VENDOR_AMD, 0xfb2 },
-//AMD_D0_SUPPORT
- { X86_VENDOR_AMD, 0x10f50 }, /* SH7-D0 */
- { X86_VENDOR_AMD, 0x10f40 },
- { X86_VENDOR_AMD, 0x10f70 },
- { X86_VENDOR_AMD, 0x10fc0 }, /* DH7-D0 */
- { X86_VENDOR_AMD, 0x10ff0 },
- { X86_VENDOR_AMD, 0x10f80 }, /* CH7-D0 */
- { X86_VENDOR_AMD, 0x10fb0 },
-//AMD_E0_SUPPORT
- { X86_VENDOR_AMD, 0x20f50 }, /* SH8-E0*/
- { X86_VENDOR_AMD, 0x20f40 },
- { X86_VENDOR_AMD, 0x20f70 },
- { X86_VENDOR_AMD, 0x20fc0 }, /* DH8-E0 */ /* DH-E3 */
- { X86_VENDOR_AMD, 0x20ff0 },
- { X86_VENDOR_AMD, 0x20f10 }, /* JH8-E1 */
- { X86_VENDOR_AMD, 0x20f30 },
- { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 */
- { X86_VENDOR_AMD, 0x20f71 },
- { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 */
- { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 */
- { X86_VENDOR_AMD, 0x20fc2 },
- { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 */
- { X86_VENDOR_AMD, 0x20f32 },
+#if CONFIG_K8_REV_F_SUPPORT == 0
+ { X86_VENDOR_AMD, 0xf40 }, /* SH-B0 (socket 754) */
+ { X86_VENDOR_AMD, 0xf50 }, /* SH-B0 (socket 940) */
+ { X86_VENDOR_AMD, 0xf51 }, /* SH-B3 (socket 940) */
+ { X86_VENDOR_AMD, 0xf58 }, /* SH-C0 (socket 940) */
+ { X86_VENDOR_AMD, 0xf48 }, /* SH-C0 (socket 754) */
+ { X86_VENDOR_AMD, 0xf5a }, /* SH-CG (socket 940) */
+ { X86_VENDOR_AMD, 0xf4a }, /* SH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xf7a }, /* SH-CG (socket 939) */
+ { X86_VENDOR_AMD, 0xfc0 }, /* DH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xfe0 }, /* DH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xff0 }, /* DH-CG (socket 939) */
+ { X86_VENDOR_AMD, 0xf82 }, /* CH-CG (socket 754) */
+ { X86_VENDOR_AMD, 0xfb2 }, /* CH-CG (socket 939) */
+
+ /* AMD D0 support */
+ { X86_VENDOR_AMD, 0x10f50 }, /* SH-D0 (socket 940) */
+ { X86_VENDOR_AMD, 0x10f40 }, /* SH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10f70 }, /* SH-D0 (socket 939) */
+ { X86_VENDOR_AMD, 0x10fc0 }, /* DH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10ff0 }, /* DH-D0 (socket 939) */
+ { X86_VENDOR_AMD, 0x10f80 }, /* CH-D0 (socket 754) */
+ { X86_VENDOR_AMD, 0x10fb0 }, /* CH-D0 (socket 939) */
+
+ /* AMD E0 support */
+ { X86_VENDOR_AMD, 0x20f50 }, /* SH-E0 */
+ { X86_VENDOR_AMD, 0x20f40 },
+ { X86_VENDOR_AMD, 0x20f70 },
+ { X86_VENDOR_AMD, 0x20fc0 }, /* DH-E3 (socket 754) */
+ { X86_VENDOR_AMD, 0x20ff0 }, /* DH-E3 (socket 939) */
+ { X86_VENDOR_AMD, 0x20f10 }, /* JH-E1 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f51 }, /* SH-E4 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f71 }, /* SH-E4 (socket 939) */
+ { X86_VENDOR_AMD, 0x20fb1 }, /* BH-E4 (socket 939) */
+ { X86_VENDOR_AMD, 0x20f42 }, /* SH-E5 (socket 754) */
+ { X86_VENDOR_AMD, 0x20ff2 }, /* DH-E6 (socket 939) */
+ { X86_VENDOR_AMD, 0x20fc2 }, /* DH-E6 (socket 754) */
+ { X86_VENDOR_AMD, 0x20f12 }, /* JH-E6 (socket 940) */
+ { X86_VENDOR_AMD, 0x20f32 }, /* JH-E6 (socket 939) */
{ X86_VENDOR_AMD, 0x30ff2 }, /* E4 ? */
#endif
-#if K8_REV_F_SUPPORT == 1
-//AMD_F0_SUPPORT
- { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 Socket F (1207): Opteron */
- { X86_VENDOR_AMD, 0x40f70 }, /* AM2: Athlon64/Athlon64 FX */
- { X86_VENDOR_AMD, 0x40f40 }, /* S1g1: Mobile Athlon64 */
- { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 Socket F (1207): Opteron Dual Core */
- { X86_VENDOR_AMD, 0x40f31 }, /* AM2: Athlon64 x2/Athlon64 FX Dual Core */
- { X86_VENDOR_AMD, 0x40f01 }, /* S1g1: Mobile Athlon64 */
- { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 Socket F (1207): Opteron Dual Core */
- { X86_VENDOR_AMD, 0x40f32 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
- { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 Socket AM2:Athlon64 x2/ Mobile Athlon64 x2 */
- { X86_VENDOR_AMD, 0x40f82 }, /* S1g1:Turion64 x2 */
- { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 Socket AM2: Athlon64 */
- { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 Socket AM2: Athlon64 */
- { X86_VENDOR_AMD, 0x40fc2 }, /* S1g1:Turion64 */
- { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 Socket F (1207): Opteron Dual Core */
- { X86_VENDOR_AMD, 0x40f33 }, /* AM2 : Opteron Dual Core/Athlon64 x2/ Athlon64 FX Dual Core */
- { X86_VENDOR_AMD, 0xc0f13 }, /* AM2 : Athlon64 FX*/
- { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 Socket AM2: Athlon64 */
+#if CONFIG_K8_REV_F_SUPPORT == 1
+ /*
+ * AMD F0 support.
+ *
+ * See Revision Guide for AMD NPT Family 0Fh Processors,
+ * Publication #33610, Revision: 3.30, February 2008.
+ *
+ * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
+ */
+ { X86_VENDOR_AMD, 0x40f50 }, /* SH-F0 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f70 }, /* SH-F0 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f40 }, /* SH-F0 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40f11 }, /* JH-F1 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f31 }, /* JH-F1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f01 }, /* JH-F1 (socket S1g1) */
+
+ { X86_VENDOR_AMD, 0x40f12 }, /* JH-F2 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f32 }, /* JH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40fb2 }, /* BH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40f82 }, /* BH-F2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40ff2 }, /* DH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x50ff2 }, /* DH-F2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x40fc2 }, /* DH-F2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x40f13 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x40f33 }, /* JH-F3 (socket AM2) */
+ { X86_VENDOR_AMD, 0x50fd3 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0xc0f13 }, /* JH-F3 (socket F/1207) */
+ { X86_VENDOR_AMD, 0x50ff3 }, /* DH-F3 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60fb1 }, /* BH-G1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60f81 }, /* BH-G1 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x60fb2 }, /* BH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60f82 }, /* BH-G2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x70ff1 }, /* DH-G1 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60ff2 }, /* DH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x70ff2 }, /* DH-G2 (socket AM2) */
+ { X86_VENDOR_AMD, 0x60fc2 }, /* DH-G2 (socket S1g1) */
+ { X86_VENDOR_AMD, 0x70fc2 }, /* DH-G2 (socket S1g1) */
#endif
{ 0, 0 },
};
-static struct cpu_driver model_fxx __cpu_driver = {
+
+static const struct cpu_driver model_fxx __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};
projects / coreboot.git / blobdiff