#include <cpu/x86/pae.h>
#include <pc80/mc146818rtc.h>
#include <cpu/x86/lapic.h>
-
-#include "../../../northbridge/amd/amdfam10/amdfam10.h"
-
+#include "northbridge/amd/amdfam10/amdfam10.h"
#include <cpu/amd/model_10xxx_rev.h>
#include <cpu/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/multicore.h>
#include <cpu/amd/model_10xxx_msr.h>
-extern device_t get_node_pci(u32 nodeid, u32 fn);
-
#define MCI_STATUS 0x401
msr_t rdmsr_amd(u32 index)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
+ msr = rdmsr(BU_CFG2_MSR);
+ /* Clear ClLinesToNbDis */
+ msr.lo &= ~(1 << 15);
+ /* Clear bit 35 as per Erratum 343 */
+ msr.hi &= ~(1 << (35-32));
+ wrmsr(BU_CFG2_MSR, msr);
+
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
msr.lo |= (1 << 0);
{ X86_VENDOR_AMD, 0x100f22 },
{ X86_VENDOR_AMD, 0x100f23 },
{ X86_VENDOR_AMD, 0x100f40 }, /* RB-C0 */
- { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
- { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
- { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
- { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
+ { X86_VENDOR_AMD, 0x100F42 }, /* RB-C2 */
+ { X86_VENDOR_AMD, 0x100F43 }, /* RB-C3 */
+ { X86_VENDOR_AMD, 0x100F52 }, /* BL-C2 */
+ { X86_VENDOR_AMD, 0x100F62 }, /* DA-C2 */
+ { X86_VENDOR_AMD, 0x100F63 }, /* DA-C3 */
+ { X86_VENDOR_AMD, 0x100F80 }, /* HY-D0 */
{ 0, 0 },
};