Remove some duplicate #include files (trivial).

[coreboot.git] / src / cpu / amd / model_10xxx / model_10xxx_init.c

diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index bf40458c3c6ad8b34e3b53afa24c0be01ee0a08a..9cd6d66e4abf3232241e1a1b9d033054ec2864b2 100644 (file)
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -27,47 +27,37 @@
 #include <cpu/x86/pae.h>
 #include <pc80/mc146818rtc.h>
 #include <cpu/x86/lapic.h>
-
-#include "../../../northbridge/amd/amdfam10/amdfam10.h"
-
+#include "northbridge/amd/amdfam10/amdfam10.h"
 #include <cpu/amd/model_10xxx_rev.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/mtrr.h>
-#include <cpu/x86/mem.h>
-#include <cpu/amd/quadcore.h>
+#include <cpu/amd/multicore.h>
 #include <cpu/amd/model_10xxx_msr.h>
 
-extern device_t get_node_pci(u32 nodeid, u32 fn);
-
-
-
 #define MCI_STATUS 0x401
 
-
-static inline msr_t rdmsr_amd(u32 index)
+msr_t rdmsr_amd(u32 index)
 {
-        msr_t result;
-        __asm__ __volatile__ (
-                "rdmsr"
-                : "=a" (result.lo), "=d" (result.hi)
-                : "c" (index), "D" (0x9c5a203a)
-                );
-        return result;
+       msr_t result;
+       __asm__ __volatile__(
+               "rdmsr"
+               :"=a"(result.lo), "=d"(result.hi)
+               :"c"(index), "D"(0x9c5a203a)
+       );
+       return result;
 }
 
-
-static inline void wrmsr_amd(u32 index, msr_t msr)
+void wrmsr_amd(u32 index, msr_t msr)
 {
-       __asm__ __volatile__ (
+       __asm__ __volatile__(
                "wrmsr"
-               : /* No outputs */
-               : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (0x9c5a203a)
-               );
+               :       /* No outputs */
+               :"c"(index), "a"(msr.lo), "d"(msr.hi), "D"(0x9c5a203a)
+       );
 }
 
-
-void model_10xxx_init(device_t dev)
+static void model_10xxx_init(device_t dev)
 {
        u8 i;
        msr_t msr;
@@ -76,8 +66,8 @@ void model_10xxx_init(device_t dev)
        u32 siblings;
 #endif
 
-       id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
-       printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
+       id = get_node_core_id(read_nb_cfg_54());        /* nb_cfg_54 can not be set */
+       printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
 
        /* Turn on caching if we haven't already */
        x86_enable_cache();
@@ -89,17 +79,17 @@ void model_10xxx_init(device_t dev)
        /* zero the machine check error status registers */
        msr.lo = 0;
        msr.hi = 0;
-       for(i=0; i < 5; i++) {
-               wrmsr(MCI_STATUS + (i * 4),msr);
+       for (i = 0; i < 5; i++) {
+               wrmsr(MCI_STATUS + (i * 4), msr);
        }
 
-
        enable_cache();
 
        /* Enable the local cpu apics */
        setup_lapic();
 
-       /* FIXME: Update CPUID name strings here */
+       /* Set the processor name string */
+       init_processor_name();
 
 #if CONFIG_LOGICAL_CPUS == 1
        siblings = cpuid_ecx(0x80000008) & 0xff;
@@ -110,17 +100,24 @@ void model_10xxx_init(device_t dev)
                wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
 
                msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-               msr.hi |= 1 << (33-32);
+               msr.hi |= 1 << (33 - 32);
                wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
        }
-       printk_debug("siblings = %02d, ", siblings);
+       printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
 #endif
 
        /* DisableCf8ExtCfg */
        msr = rdmsr(NB_CFG_MSR);
-       msr.hi &= ~(1 << (46-32));
+       msr.hi &= ~(1 << (46 - 32));
        wrmsr(NB_CFG_MSR, msr);
 
+       msr = rdmsr(BU_CFG2_MSR);
+       /* Clear ClLinesToNbDis */
+       msr.lo &= ~(1 << 15);
+       /* Clear bit 35 as per Erratum 343 */
+       msr.hi &= ~(1 << (35-32));
+       wrmsr(BU_CFG2_MSR, msr);
+
        /* Write protect SMM space with SMMLOCK. */
        msr = rdmsr(HWCR_MSR);
        msr.lo |= (1 << 0);
@@ -131,6 +128,7 @@ void model_10xxx_init(device_t dev)
 static struct device_operations cpu_dev_ops = {
        .init = model_10xxx_init,
 };
+
 static struct cpu_device_id cpu_table[] = {
 //AMD_GH_SUPPORT
        { X86_VENDOR_AMD, 0x100f00 },           /* SH-F0 L1 */
@@ -140,9 +138,17 @@ static struct cpu_device_id cpu_table[] = {
        { X86_VENDOR_AMD, 0x100f2A },
        { X86_VENDOR_AMD, 0x100f22 },
        { X86_VENDOR_AMD, 0x100f23 },
+       { X86_VENDOR_AMD, 0x100f40 },           /* RB-C0 */
+       { X86_VENDOR_AMD, 0x100F42 },           /* RB-C2 */
+       { X86_VENDOR_AMD, 0x100F43 },           /* RB-C3 */
+       { X86_VENDOR_AMD, 0x100F52 },           /* BL-C2 */
+       { X86_VENDOR_AMD, 0x100F62 },           /* DA-C2 */
+       { X86_VENDOR_AMD, 0x100F63 },           /* DA-C3 */
+       { X86_VENDOR_AMD, 0x100F80 },           /* HY-D0 */
        { 0, 0 },
 };
-static struct cpu_driver model_10xxx __cpu_driver = {
-       .ops      = &cpu_dev_ops,
+
+static const struct cpu_driver model_10xxx __cpu_driver = {
+       .ops      = &cpu_dev_ops,
        .id_table = cpu_table,
 };