Trivial - remove stray characters from a comment block.

[coreboot.git] / src / cpu / amd / model_10xxx / init_cpus.c

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index cce44d78698082e4254145d2e541faf972f0715a..b5947c9d33be7f5fe3e12dd17af57efb6decae06 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -18,6 +18,15 @@
  */
 
 #include "defaults.h"
+#include <stdlib.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/porting.h>
+
+#include <cpu/x86/mtrr/earlymtrr.c>
+#include <northbridge/amd/amdfam10/raminit_amdmct.c>
 
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID
@@ -30,7 +39,6 @@
        #define SET_FIDVID_CORE0_ONLY 0
 #endif
 
-void update_microcode(u32 cpu_deviceid);
 static void prep_fid_change(void);
 static void init_fidvid_stage2(u32 apicid, u32 nodeid);
 void cpuSetAMDMSR(void);
@@ -101,13 +109,12 @@ static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap,
        /* get_nodes define in ht_wrapper.c */
        nodes = get_nodes();
 
-       disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1
-       if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {        // 0 mean multi core
+       if (!CONFIG_LOGICAL_CPUS ||
+           read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) {        // 0 means multi core
                disable_siblings = 1;
+       } else {
+               disable_siblings = 0;
        }
-#endif
 
        /* Assume that all node are same stepping, otherwise we can use use
           nb_cfg_54 from bsp for all nodes */
@@ -237,7 +244,7 @@ static void wait_ap_started(u32 ap_apicid, void *gp)
        }
 }
 
-static void wait_all_other_cores_started(u32 bsp_apicid)
+void wait_all_other_cores_started(u32 bsp_apicid)
 {
        // all aps other than core0
        printk(BIOS_DEBUG, "started ap apicid: ");
@@ -245,12 +252,11 @@ static void wait_all_other_cores_started(u32 bsp_apicid)
        printk(BIOS_DEBUG, "\n");
 }
 
-static void allow_all_aps_stop(u32 bsp_apicid)
+void allow_all_aps_stop(u32 bsp_apicid)
 {
        /* Called by the BSP to indicate AP can stop */
 
-       /* FIXME Do APs use this?
-          Looks like wait_till_sysinfo_in_ram is used instead. */
+       /* FIXME Do APs use this? */
 
        // allow aps to stop use 6 bits for state
        lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x14);
@@ -388,15 +394,11 @@ static u32 init_cpus(u32 cpu_init_detectedx)
                }
 #endif
 
-               /* AP is ready, Wait for the BSP to get memory configured */
-               /* FIXME: many cores spinning on node0 pci register seems to be bad.
-                * Why do we need to wait? These APs are just going to go sit in a hlt.
-                */
-               //wait_till_sysinfo_in_ram();
-
+               /* AP is ready, configure MTRRs and go to sleep */
                set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
 
                STOP_CAR_AND_CPU();
+
                printk(BIOS_DEBUG,
                       "\nAP %02x should be halted but you are reading this....\n",
                       apicid);
@@ -415,7 +417,7 @@ static u32 is_core0_started(u32 nodeid)
        return htic;
 }
 
-static void wait_all_core0_started(void)
+void wait_all_core0_started(void)
 {
        /* When core0 is started, it will distingush_cpu_resets
         * So wait for that to finish */
@@ -875,7 +877,7 @@ static void cpuSetAMDPCI(u8 node)
                        /* HT Phy settings either apply to both sublinks or have
                         * separate registers for sublink zero and one, so there
                         * will be two table entries. So, here we only loop
-                        cd t   * through the sublink zeros in function zero.
+                        * through the sublink zeros in function zero.
                         */
                        for (j = 0; j < 4; j++) {
                                if (AMD_CpuFindCapability(node, j, &offset)) {
@@ -905,6 +907,7 @@ static void cpuSetAMDPCI(u8 node)
        printk(BIOS_DEBUG, " done\n");
 }
 
+#ifdef UNUSED_CODE
 static void cpuInitializeMCA(void)
 {
        /* Clears Machine Check Architecture (MCA) registers, which power on
@@ -932,6 +935,7 @@ static void cpuInitializeMCA(void)
                }
        }
 }
+#endif
 
 /**
  * finalize_node_setup()
@@ -971,3 +975,5 @@ static void finalize_node_setup(struct sys_info *sysinfo)
        }
 #endif
 }
+
+#include "fidvid.c"