Fix Fam10 MMCONF_SUPPORT_DEFAULT setting.

[coreboot.git] / src / cpu / amd / model_10xxx / Kconfig

diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 3f80baf9e6a3db9a3368bb3bdceea7d7653311a3..221d0449ac5f4157805f35f090d718d6b790f36f 100644 (file)
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -1,27 +1,86 @@
 config CPU_AMD_MODEL_10XXX
        bool
-       select HAVE_INIT_TIMER
-       select HAVE_MOVNTI
-       select USE_PRINTK_IN_CAR
-       select USE_DCACHE_RAM
+       select SSE
+       select SSE2
+       select MMCONF_SUPPORT_DEFAULT
 
+if CPU_AMD_MODEL_10XXX
 config CPU_ADDR_BITS
        int
        default 48
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_BASE
        hex
        default 0xc4000
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_SIZE
        hex
        default 0x0c000
-       depends on CPU_AMD_MODEL_10XXX
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
        default 0x04000
-       depends on CPU_AMD_MODEL_10XXX
 
+config UDELAY_IO
+       bool
+       default n
+
+config SET_FIDVID
+       bool
+       default y
+
+if SET_FIDVID
+config SET_FIDVID_DEBUG
+       bool
+       default y
+
+config SET_FIDVID_STORE_AP_APICID_AT_FIRST
+       bool
+       default y
+
+config SET_FIDVID_CORE0_ONLY
+       bool
+       default n
+
+# 0: all cores
+# 1: core 0 only
+# 2: all but core 0
+config SET_FIDVID_CORE_RANGE
+       int
+       default 0
+
+endif  # SET_FIDVID
+
+config UPDATE_CPU_MICROCODE
+       bool
+       default y
+
+config UPDATE_CPU_MICROCODE
+       bool "Update CPU microcode"
+       default y
+       depends on EXPERT && CPU_AMD_MODEL_10XXX
+       help
+         Select this to apply patches to the CPU microcode provided by
+         AMD without source, and distributed with coreboot, to address
+         issues in the CPU post production.
+
+         Microcode updates distributed with coreboot are not necessarily
+         the latest version available from AMD. Updates are only applied
+         if they are newer than the microcode already in your CPU.
+
+         Unselect this to let Fam10h CPUs run with microcode as shipped
+         from factory. No binary microcode patches will be included in the
+         coreboot image in that case, which can help with creating an image
+         for which complete source code is available, which in turn might
+         simplify license compliance.
+
+         Microcode updates intend to solve issues that have been discovered
+         after CPU production. The common case is that systems work as
+         intended with updated microcode, but we have also seen cases where
+         issues were solved by not applying the microcode updates.
+
+         Note that some operating system include these same microcode
+         patches, so you may need to also disable microcode updates in
+         your operating system in order for this option to matter.
+
+endif  # CPU_AMD_MODEL_10XXX