#include <console/console.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
-#include <cpu/amd/dualcore.h>
+#include <cpu/amd/multicore.h>
#include <device/device.h>
#include <device/pci.h>
#include <pc80/mc146818rtc.h>
#include <smp/spinlock.h>
#include <cpu/x86/mtrr.h>
-#include "../model_fxx/model_fxx_msr.h"
-#include "../../../northbridge/amd/amdk8/cpu_rev.c"
+#include <cpu/amd/model_fxx_msr.h>
+#include <cpu/amd/model_fxx_rev.h>
+#include <cpu/amd/amdk8_sysconf.h>
-static int first_time = 1;
static int disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-int is_e0_later_in_bsp(int nodeid)
-{
- uint32_t val;
- uint32_t val_old;
- int e0_later;
- if(nodeid==0) { // we don't need to do that for node 0 in core0/node0
- return !is_cpu_pre_e0();
- }
- // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
- device_t dev;
- dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid,2));
- if(!dev) return 0;
- val_old = pci_read_config32(dev, 0x80);
- val = val_old;
- val |= (1<<3);
- pci_write_config32(dev, 0x80, val);
- val = pci_read_config32(dev, 0x80);
- e0_later = !!(val & (1<<3));
- if(e0_later) { // pre_e0 bit 3 always be 0 and can not be changed
- pci_write_config32(dev, 0x80, val_old); // restore it
- }
-
- return e0_later;
-}
-
-unsigned int read_nb_cfg_54(void)
-{
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- return ( ( msr.hi >> (54-32)) & 1);
-}
-
-struct node_core_id get_node_core_id(unsigned int nb_cfg_54) {
- struct node_core_id id;
- // get the apicid via cpuid(1) ebx[27:24]
- if(nb_cfg_54) {
- // when NB_CFG[54] is set, nodid = ebx[27:25], coreid = ebx[24]
- id.coreid = (cpuid_ebx(1) >> 24) & 0xf;
- id.nodeid = (id.coreid>>1);
- id.coreid &= 1;
- } else { // single core should be here too
- // when NB_CFG[54] is clear, nodeid = ebx[26:24], coreid = ebx[27]
- id.nodeid = (cpuid_ebx(1) >> 24) & 0xf;
- id.coreid = (id.nodeid>>3);
- id.nodeid &= 7;
- }
- return id;
-
-
-}
+#include "dualcore_id.c"
static int get_max_siblings(int nodes)
{
for(nodeid=0; nodeid<nodes; nodeid++){
int j;
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
- j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
+ j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
if(siblings < j) {
siblings = j;
}
}
-
+
return siblings;
}
dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
val = pci_read_config32(dev, 0x68);
val |= (1<<17)|(1<<18);
- pci_write_config32(dev, 0x68, val);
+ pci_write_config32(dev, 0x68, val);
}
}
unsigned nb_cfg_54;
int bsp_apic_id = lapicid(); // bsp apicid
- int disable_siblings = !CONFIG_LOGICAL_CPUS;
-
-
- get_option(&disable_siblings, "dual_core");
+ get_option(&disable_siblings, "multi_core");
//get the nodes number
dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
if(bsp_apic_id > 0) { // io apic could start from 0
return 0;
} else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) ) { // enabled ext id but bsp = 0
- if(!disable_siblings) { return siblings + 1; }
- else { return 1; }
+ return 1;
}
nb_cfg_54 = read_nb_cfg_54();
#if 0
- //it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
+ //it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it.
if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
//we need to check if e0 single core is there
int i;
//4:10 for two way 8:12 for four way 16:16 for eight way
//Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
- apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
+ apicid_base = nb_cfg_54 ? (siblings+1) * nodes : 8 * siblings + nodes;
}
else {
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
- printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
+ printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
enable_apic_ext_id(nodes);
}
-
+
return apicid_base;
}
+
#if 0
+static int first_time = 1;
+
void amd_sibling_init(device_t cpu)
{
unsigned i, siblings;
/* On the bootstrap processor see if I want sibling cpus enabled */
if (first_time) {
first_time = 0;
- get_option(&disable_siblings, "dual_core");
+ get_option(&disable_siblings, "multi_core");
}
result = cpuid(0x80000008);
/* See how many sibling cpus we have */
}
#if 1
- printk_debug("CPU: %u %d siblings\n",
- cpu->path.u.apic.apic_id,
+ printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
+ cpu->path.apic.apic_id,
siblings);
#endif
- nb_cfg_54 = read_nb_cfg_54();
+ nb_cfg_54 = read_nb_cfg_54();
#if 1
id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
/* See if I am a sibling cpu */
- //if ((cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
- //if ( ( (cpu->path.u.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
+ //if ((cpu->path.apic.apic_id>>(nb_cfg_54?0:3)) & siblings ) { // siblings = 1, 3, 7, 15,....
+ //if ( ( (cpu->path.apic.apic_id>>(nb_cfg_54?0:3)) % (siblings+1) ) != 0 ) {
if(id.coreid != 0) {
if (disable_siblings) {
cpu->enabled = 0;
return;
}
#endif
-
+
/* I am the primary cpu start up my siblings */
for(i = 1; i <= siblings; i++) {
device_t new;
/* Build the cpu device path */
cpu_path.type = DEVICE_PATH_APIC;
- cpu_path.u.apic.apic_id = cpu->path.u.apic.apic_id + i * (nb_cfg_54?1:8);
+ cpu_path.apic.apic_id = cpu->path.apic.apic_id + i * (nb_cfg_54?1:8);
+ if(id.nodeid == 0) {
+ // need some special processing, because may the bsp is not lifted, but the core1 is lifted
+ //defined in northbridge.c
+ if(sysconf.enabled_apic_ext_id && (!sysconf.lift_bsp_apicid)) {
+ cpu->path.apic.apic_id += sysconf.apicid_offset;
+ }
+
+ }
+
/* See if I can find the cpu */
new = find_dev_path(cpu->bus, &cpu_path);
new->initialized = 0;
}
+ new->path.apic.node_id = cpu->path.apic.node_id;
+ new->path.apic.core_id = i;
+
#if 1
- printk_debug("CPU: %u has sibling %u\n",
- cpu->path.u.apic.apic_id,
- new->path.u.apic.apic_id);
+ printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
+ cpu->path.apic.apic_id,
+ new->path.apic.apic_id);
#endif
- /* Start the new cpu */
+
if(new->enabled && !new->initialized)
start_cpu(new);
}
-
}
#endif
projects / coreboot.git / blobdiff