Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / cpu / amd / dualcore / amd_sibling.c

diff --git a/src/cpu/amd/dualcore/amd_sibling.c b/src/cpu/amd/dualcore/amd_sibling.c
index 45d12d8288c5f04da0f299aa61b916c226c38566..af96265d6c3dfd6e8a3093502f667e09e09c297b 100644 (file)
--- a/src/cpu/amd/dualcore/amd_sibling.c
+++ b/src/cpu/amd/dualcore/amd_sibling.c
@@ -3,7 +3,7 @@
 #include <console/console.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <cpu/amd/dualcore.h>
+#include <cpu/amd/multicore.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <pc80/mc146818rtc.h>
@@ -13,8 +13,7 @@
 #include <cpu/amd/model_fxx_rev.h>
 #include <cpu/amd/amdk8_sysconf.h>
 
-static int first_time = 1;
-static uint32_t disable_siblings = !CONFIG_LOGICAL_CPUS;
+static int disable_siblings = !CONFIG_LOGICAL_CPUS;
 
 #include "dualcore_id.c"
 
@@ -28,12 +27,12 @@ static int get_max_siblings(int nodes)
        for(nodeid=0; nodeid<nodes; nodeid++){
                int j;
                dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 3));
-               j = (pci_read_config32(dev, 0xe8) >> 12) & 3; 
+               j = (pci_read_config32(dev, 0xe8) >> 12) & 3;
                if(siblings < j) {
                        siblings = j;
                }
        }
-       
+
        return siblings;
 }
 
@@ -48,7 +47,7 @@ static void enable_apic_ext_id(int nodes)
                 dev = dev_find_slot(0, PCI_DEVFN(0x18+nodeid, 0));
                 val = pci_read_config32(dev, 0x68);
                val |= (1<<17)|(1<<18);
-               pci_write_config32(dev, 0x68, val); 
+               pci_write_config32(dev, 0x68, val);
         }
 }
 
@@ -62,7 +61,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
        unsigned nb_cfg_54;
         int bsp_apic_id = lapicid(); // bsp apicid
 
-        get_option("dual_core", &disable_siblings);
+        get_option(&disable_siblings, "multi_core");
 
         //get the nodes number
         dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
@@ -71,15 +70,15 @@ unsigned get_apicid_base(unsigned ioapic_num)
        siblings = get_max_siblings(nodes);
 
        if(bsp_apic_id > 0) { // io apic could start from 0
-               return 0;  
+               return 0;
        } else if(pci_read_config32(dev, 0x68) & ( (1<<17) | (1<<18)) )  { // enabled ext id but bsp = 0
-               return 1; 
+               return 1;
        }
 
        nb_cfg_54 = read_nb_cfg_54();
 
 #if 0
-       //it is for all e0 single core and nc_cfg_54 low is set, but in the auto.c stage we do not set that bit for it.
+       //it is for all e0 single core and nc_cfg_54 low is set, but in the romstage.c stage we do not set that bit for it.
        if(nb_cfg_54 && (!disable_siblings) && (siblings == 0)) {
                //we need to check if e0 single core is there
                int i;
@@ -101,7 +100,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
                //4:10 for two way  8:12 for four way 16:16 for eight way
                //Use CONFIG_MAX_PHYSICAL_CPUS instead of nodes for better consistency?
-               apicid_base = nb_cfg_54 ? (siblings+1) * nodes :  8 * siblings + nodes; 
+               apicid_base = nb_cfg_54 ? (siblings+1) * nodes :  8 * siblings + nodes;
 
        }
        else {
@@ -110,13 +109,16 @@ unsigned get_apicid_base(unsigned ioapic_num)
 
        if((apicid_base+ioapic_num-1)>0xf) {
                // We need to enable APIC EXT ID
-               printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set ENABLE_APIC_EXT_ID in auto.c so you can spare 16 id for ioapic\r\n");
+               printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\n");
                enable_apic_ext_id(nodes);
        }
-       
+
        return apicid_base;
 }
+
 #if 0
+static int first_time = 1;
+
 void amd_sibling_init(device_t cpu)
 {
        unsigned i, siblings;
@@ -127,7 +129,7 @@ void amd_sibling_init(device_t cpu)
        /* On the bootstrap processor see if I want sibling cpus enabled */
        if (first_time) {
                first_time = 0;
-               get_option("dual_core", &disable_siblings);
+               get_option(&disable_siblings, "multi_core");
        }
        result = cpuid(0x80000008);
        /* See how many sibling cpus we have */
@@ -138,12 +140,12 @@ void amd_sibling_init(device_t cpu)
        }
 
 #if 1
-       printk_debug("CPU: %u %d siblings\n",
+       printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
                cpu->path.apic.apic_id,
                siblings);
 #endif
 
-       nb_cfg_54 = read_nb_cfg_54(); 
+       nb_cfg_54 = read_nb_cfg_54();
 #if 1
        id = get_node_core_id(nb_cfg_54); // pre e0 nb_cfg_54 can not be set
 
@@ -157,7 +159,7 @@ void amd_sibling_init(device_t cpu)
                 return;
        }
 #endif
-               
+
        /* I am the primary cpu start up my siblings */
 
        for(i = 1; i <= siblings; i++) {
@@ -189,7 +191,7 @@ void amd_sibling_init(device_t cpu)
                 new->path.apic.core_id = i;
 
 #if 1
-               printk_debug("CPU: %u has sibling %u\n", 
+               printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
                        cpu->path.apic.apic_id,
                        new->path.apic.apic_id);
 #endif