Fix all warnings in the tree

[coreboot.git] / src / cpu / amd / car / cache_as_ram.inc

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index d09934111bdaad8ed133aa16f680b46f44be9f3e..aedb2fd564e8e5a962a986cd35a9c9d093c1a1f4 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -37,21 +37,19 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 /*
- XMM map:
-    xmm1: cpu family
-    xmm2: fam10 comparison value
-    xmm3: backup ebx
-*/
+ * XMM map:
+ *   xmm1: cpu family
+ *   xmm2: fam10 comparison value
+ *   xmm3: backup ebx
+ */
 
        /* Save the BIST result */
        movl    %eax, %ebp
 
-       /*for normal part %ebx already contain cpu_init_detected from fallback call */
+       /* for normal part %ebx already contain cpu_init_detected from fallback call */
 
 cache_as_ram_setup:
-
-       movb    $0xA0, %al
-       outb    %al, $0x80
+       post_code(0xa0)
 
        /* enable SSE */
        movl %cr4, %eax
@@ -71,9 +69,6 @@ cache_as_ram_setup:
        cvtsi2sd %eax, %xmm2
        cvtsd2si %xmm3, %ebx
 
-       /* hope we can skip the double set for normal part */
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
-
        /* check if cpu_init_detected */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
@@ -118,7 +113,8 @@ cache_as_ram_setup:
 CAR_FAM10_out:
 
        /* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
-          Re-enable it in after RAM is initialized and before CAR is disabled */
+        * Re-enable it in after RAM is initialized and before CAR is disabled
+        */
        movl    $0xc001102a, %ecx
        rdmsr
        bts     $15, %eax
@@ -248,15 +244,6 @@ clear_fixed_var_mtrr_out:
        xorl    %edx, %edx
        movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
-#endif /*  CONFIG_USE_FAILOVER_IMAGE == 1*/
-
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 0)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 0))
-       /* disable cache */
-       movl    %cr0, %eax
-       orl     $(0x1 << 30), %eax
-       movl    %eax, %cr0
-
-#endif
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
        /* enable write base caching so we can do execute in place
@@ -283,7 +270,6 @@ wbcache_post_fam10_setup:
        wrmsr
 #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
        /* Set the default memory type and enable fixed and variable MTRRs */
        movl    $MTRRdefType_MSR, %ecx
        xorl    %edx, %edx
@@ -296,10 +282,8 @@ wbcache_post_fam10_setup:
        rdmsr
        orl     $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
        wrmsr
-#endif
 
-       movb    $0xA1, %al
-       outb    %al, $0x80
+       post_code(0xa1)
 
        /* enable cache */
        movl    %cr0, %eax
@@ -315,10 +299,8 @@ wbcache_post_fam10_setup:
        jnc     CAR_FAM10_ap
 fam10_end_part1:
 
-       movb    $0xA2, %al
-       outb    %al, $0x80
+       post_code(0xa2)
 
-#if ((CONFIG_HAVE_FAILOVER_BOOT == 1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT == 0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
        /* Read the range with lodsl*/
        cld
        movl    $CacheBase, %esi
@@ -331,14 +313,11 @@ fam10_end_part1:
        xorl    %eax, %eax
        rep     stosl
 
-#endif /*CONFIG_USE_FAILOVER_IMAGE == 1*/
-
        /* set up the stack pointer */
        movl    $(CacheBase + CacheSize - GlobalVarSize), %eax
        movl    %eax, %esp
 
-       movb    $0xA3, %al
-       outb    %al, $0x80
+       post_code(0xa3)
 
        jmp     CAR_FAM10_ap_out
 CAR_FAM10_ap:
@@ -380,13 +359,11 @@ roll_cfg:
        /* retrive init detected */
        movl    %esi, %ebx
 
-       movb    $0xA4, %al
-       outb    %al, $0x80
+       post_code(0xa4)
 
 CAR_FAM10_ap_out:
 
-       movb    $0xA5, %al
-       outb    %al, $0x80
+       post_code(0xa5)
 
        /* disable SSE */
        movl %cr4, %eax
@@ -403,8 +380,7 @@ CAR_FAM10_ap_out:
        call    cache_as_ram_main
        /* We will not go back */
 
-       movb    $0xAF, %al      /* Should never see this postcode */
-       outb    %al, $0x80
+       post_code(0xaf)         /* Should never see this postcode */
 
 fixed_mtrr_msr:
        .long   0x250, 0x258, 0x259