* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define CacheSize DCACHE_RAM_SIZE
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
#define CacheBase (0xd0000 - CacheSize)
/* leave some space for global variable to pass to RAM stage */
-#define GlobalVarSize DCACHE_RAM_GLOBAL_VAR_SIZE
+#define GlobalVarSize CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-#if CAR_FAM10 == 1
+/* for CAR with FAM10 */
#define CacheSizeAPStack 0x400 /* 1K */
-#endif
+
+#define MSR_FAM10 0xC001102A
+
+#define jmp_if_k8(x) comisd %xmm2, %xmm1; jb x
+
+#define CPUID_MASK 0x0ff00f00
+#define CPUID_VAL_FAM10_ROTATED 0x0f000010
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
+/*
+ * XMM map:
+ * xmm1: cpu family
+ * xmm2: fam10 comparison value
+ * xmm3: backup ebx
+ */
/* Save the BIST result */
movl %eax, %ebp
- /*for normal part %ebx already contain cpu_init_detected from fallback call */
+ /* for normal part %ebx already contain cpu_init_detected from fallback call */
cache_as_ram_setup:
+ post_code(0xa0)
- movb $0xA0, %al
- outb %al, $0x80
+ /* enable SSE */
+ movl %cr4, %eax
+ orl $(3<<9), %eax
+ movl %eax, %cr4
- /* hope we can skip the double set for normal part */
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
+ /* figure out cpu family */
+ cvtsi2sd %ebx, %xmm3
+ movl $0x01, %eax
+ cpuid
+ /* base family is bits 8..11, extended family is bits 20..27 */
+ andl $CPUID_MASK, %eax
+ /* reorder bits for easier comparison by value */
+ roll $0x10, %eax
+ cvtsi2sd %eax, %xmm1
+ movl $CPUID_VAL_FAM10_ROTATED, %eax
+ cvtsi2sd %eax, %xmm2
+ cvtsd2si %xmm3, %ebx
/* check if cpu_init_detected */
movl $MTRRdefType_MSR, %ecx
andl $(1 << 11), %eax
movl %eax, %ebx /* We store the status */
-#if CAR_FAM10 == 1
+ jmp_if_k8(CAR_FAM10_out_post_errata)
+
/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to node0 */
/* Only BSP needed, for other nodes set during HT/memory init. */
CAR_FAM10_out:
-#endif
-
-#if CAR_FAM10 == 1
/* Errata 193: Disable clean copybacks to L3 cache to allow cached ROM.
- Re-enable it in after RAM is initialized and before CAR is disabled */
+ * Re-enable it in after RAM is initialized and before CAR is disabled
+ */
movl $0xc001102a, %ecx
rdmsr
bts $15, %eax
wrmsr
-#endif
+
+ /* Erratum 343, RevGuide for Fam10h, Pub#41322 Rev. 3.33 */
+
+ /* read-address has to be stored in the ecx register */
+ movl $MSR_FAM10, %ecx
+
+ /* execute special read command for msr-register. Result is then in the EDX:EAX-registers (MSBs in EDX) */
+ rdmsr
+
+ /* Set bit 35 to 1 in EAX */
+ bts $35, %eax
+
+ /* write back the modified register EDX:EAX to the MSR specified in ECX */
+ wrmsr
+
+ /* Erratum 343 end */
+
+CAR_FAM10_out_post_errata:
/* Set MtrrFixDramModEn for clear fixed mtrr */
enable_fixed_mtrr_dram_modify:
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
- jz clear_fixed_var_mtrr_out
+ jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
- jmp clear_fixed_var_mtrr
+ jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment.
* macro will have a monotonically increasing segs parameter.
*/
xorl \reg, \reg
-#if CAR_FAM10 == 1
-.elseif \segs == 1
+.else
+ jmp_if_k8(1f)
+
+.if \segs == 1
movl $0x1e000000, \reg /* WB MEM type */
.elseif \segs == 2
movl $0x1e1e0000, \reg /* WB MEM type */
movl $0x1e1e1e00, \reg /* WB MEM type */
.elseif \segs >= 4
movl $0x1e1e1e1e, \reg /* WB MEM type */
-#else
-.elseif \segs == 1
+.endif
+ jmp 2f
+1:
+.if \segs == 1
movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2
movl $0x06060000, \reg /* WB IO type */
movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4
movl $0x06060606, \reg /* WB IO type */
-#endif
.endif
+2:
+.endif /* if \segs <= 0 */
.endm
/* size is the cache size in bytes we want to use for CAR.
#error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.
#endif
-#if CacheSize > 0x8000
- /* enable caching for 32K-64K using fixed mtrr */
- movl $0x268, %ecx /* fix4k_c0000*/
+#if CacheSize > 0x8000
+ /* enable caching for 32K-64K using fixed mtrr */
+ movl $0x268, %ecx /* fix4k_c0000*/
simplemask CacheSize, 0x8000
- wrmsr
+ wrmsr
#endif
- /* enable caching for 0-32K using fixed mtrr */
- movl $0x269, %ecx /* fix4k_c8000*/
+ /* enable caching for 0-32K using fixed mtrr */
+ movl $0x269, %ecx /* fix4k_c8000*/
simplemask CacheSize, 0
wrmsr
/* enable memory access for first MBs using top_mem */
movl $TOP_MEM, %ecx
xorl %edx, %edx
- movl $(((CONFIG_LB_MEM_TOPK << 10) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
+ movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
wrmsr
-#endif /* USE_FAILOVER_IMAGE == 1*/
-
-
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 0)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 0))
- /* disable cache */
- movl %cr0, %eax
- orl $(1 << 30),%eax
- movl %eax, %cr0
-
-#endif
-#if defined(XIP_ROM_SIZE) && defined(XIP_ROM_BASE)
+#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
/* enable write base caching so we can do execute in place
* on the flash rom.
*/
movl $0x202, %ecx
xorl %edx, %edx
- movl $(XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+
+#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+ movl $REAL_XIP_ROM_BASE, %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
movl $0x203, %ecx
- movl $((1 << (CPU_ADDR_BITS - 32)) - 1), %edx /* AMD 40 bit for K8, 48 bit for GH */
- movl $(~(XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
+ jmp_if_k8(wbcache_post_fam10_setup)
+ movl $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
+wbcache_post_fam10_setup:
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
wrmsr
-#endif /* XIP_ROM_SIZE && XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
/* Set the default memory type and enable fixed and variable MTRRs */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
/* Enable the MTRRs and IORRs in SYSCFG */
movl $SYSCFG_MSR, %ecx
rdmsr
- orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
+ orl $(SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn), %eax
wrmsr
-#endif
- movb $0xA1, %al
- outb %al, $0x80
+ post_code(0xa1)
/* enable cache */
movl %cr0, %eax
andl $0x9fffffff, %eax
movl %eax, %cr0
+ jmp_if_k8(fam10_end_part1)
-#if CAR_FAM10 == 1
/* So we need to check if it is BSP */
movl $0x1b, %ecx
rdmsr
bt $8, %eax /*BSC */
jnc CAR_FAM10_ap
-#endif
+fam10_end_part1:
- movb $0xA2, %al
- outb %al, $0x80
+ post_code(0xa2)
-#if ((HAVE_FAILOVER_BOOT == 1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT == 0) && (USE_FALLBACK_IMAGE == 1))
- /* Read the range with lodsl*/
+ /* Read the range with lodsl*/
cld
movl $CacheBase, %esi
movl $(CacheSize >> 2), %ecx
- rep lodsl
+ rep lodsl
+
/* Clear the range */
movl $CacheBase, %edi
movl $(CacheSize >> 2), %ecx
xorl %eax, %eax
- rep stosl
-
-#endif /*USE_FAILOVER_IMAGE == 1*/
+ rep stosl
/* set up the stack pointer */
movl $(CacheBase + CacheSize - GlobalVarSize), %eax
movl %eax, %esp
- movb $0xA3, %al
- outb %al, $0x80
-
-#if CAR_FAM10 == 1
+ post_code(0xa3)
jmp CAR_FAM10_ap_out
CAR_FAM10_ap:
/* retrive init detected */
movl %esi, %ebx
- movb $0xA4, %al
- outb %al, $0x80
+ post_code(0xa4)
CAR_FAM10_ap_out:
-#endif
- movb $0xA5, %al
- outb %al, $0x80
+ post_code(0xa5)
+
+ /* disable SSE */
+ movl %cr4, %eax
+ andl $~(3<<9), %eax
+ movl %eax, %cr4
/* Restore the BIST result */
movl %ebp, %eax
call cache_as_ram_main
/* We will not go back */
- movb $0xAF, %al /* Should never see this postcode */
- outb %al, $0x80
+ post_code(0xaf) /* Should never see this postcode */
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
projects / coreboot.git / blobdiff