Fix timer frequency detection on Sandybridge

[coreboot.git] / src / cpu / Kconfig

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index c33618570546ee8df6e729571af005700af985ef..ec10a97983adcca1bf9442043d8f8c5054cd2587 100644 (file)
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -1,12 +1,13 @@
+if ARCH_X86
+
 source src/cpu/amd/Kconfig
-source src/cpu/emulation/Kconfig
 source src/cpu/intel/Kconfig
 source src/cpu/via/Kconfig
 source src/cpu/x86/Kconfig
 
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
        bool
-       default n
+       default !ROMCC
 
 config DCACHE_RAM_BASE
        hex
@@ -30,6 +31,12 @@ config SMP
          This option is used to enable certain functions to make coreboot
          work correctly on symmetric multi processor (SMP) systems.
 
+config AP_SIPI_VECTOR
+       hex
+       default 0xfffff000
+       help
+         This must equal address of ap_sipi_vector from bootblock build.
+
 config MMX
        bool
        help
@@ -58,3 +65,5 @@ config VAR_MTRR_HOLE
        help
                Unset this if you don't want the MTRR code to use
                subtractive MTRRs
+
+endif # ARCH_X86