MCP55: Cosmetic fixes, switch to u8 et al.

[coreboot.git] / src / cpu / Kconfig

diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index c0cf76887f81d7ba81115b3e8b4d730134a46ee7..6e6518618b85add382f81b1a50079ce0b6511ddf 100644 (file)
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -1,20 +1,19 @@
+if ARCH_X86
+
 source src/cpu/amd/Kconfig
-source src/cpu/emulation/Kconfig
 source src/cpu/intel/Kconfig
 source src/cpu/via/Kconfig
 source src/cpu/x86/Kconfig
 
-config USE_DCACHE_RAM
+config CACHE_AS_RAM
        bool
-       default n
+       default !ROMCC
 
 config DCACHE_RAM_BASE
        hex
-       default 0xffdf8000 if CPU_INTEL_CORE
 
 config DCACHE_RAM_SIZE
        hex
-       default 0x8000 if CPU_INTEL_CORE
 
 config DCACHE_RAM_GLOBAL_VAR_SIZE
        hex
@@ -48,6 +47,7 @@ config SSE
 
 config SSE2
        bool
+       default n
        help
          Select SSE2 in your socket or model Kconfig if your CPU has SSE2
          streaming SIMD instructions. Some parts of coreboot can be built
@@ -59,3 +59,5 @@ config VAR_MTRR_HOLE
        help
                Unset this if you don't want the MTRR code to use
                subtractive MTRRs
+
+endif # ARCH_X86