Add support for 32bit PCI BIOS entry.

[seabios.git] / src / config.h

diff --git a/src/config.h b/src/config.h
index 494fe8d5408b2846c60f3bf447fa1cdefa3fc111..1450bf7d0c2c368e887a6be78dae041131d8b193 100644 (file)
--- a/src/config.h
+++ b/src/config.h
@@ -12,8 +12,6 @@
 #define CONFIG_APPNAME6 "BOCHS "
 #define CONFIG_APPNAME4 "BXPC"
 
-// Configure for use with KVM.
-#define CONFIG_KVM 0
 // Configure as a coreboot payload.
 #define CONFIG_COREBOOT 0
 
@@ -24,10 +22,24 @@
 // Screen writes are also sent to debug ports.
 #define CONFIG_SCREEN_AND_DEBUG 1
 
+// Support running hardware initialization in parallel
+#define CONFIG_THREADS 1
+// Allow hardware init to run in parallel with optionrom execution
+#define CONFIG_THREAD_OPTIONROMS 0
 // Support int13 disk/floppy drive functions
 #define CONFIG_DRIVES 1
 // Support floppy drive access
 #define CONFIG_FLOPPY 1
+// Support USB devices
+#define CONFIG_USB 1
+// Support USB UHCI controllers
+#define CONFIG_USB_UHCI 1
+// Support USB OHCI controllers
+#define CONFIG_USB_OHCI 1
+// Support USB keyboards
+#define CONFIG_USB_KEYBOARD 1
+// Support PS2 ports (keyboard and mouse)
+#define CONFIG_PS2PORT 1
 // Support for IDE disk code
 #define CONFIG_ATA 1
 // Use 32bit PIO accesses on ATA (minor optimization on PCI transfers)
@@ -61,7 +73,7 @@
 // Disable A20 on 16bit boot
 #define CONFIG_DISABLE_A20 0
 // Support for int15c2 mouse calls
-#define CONFIG_PS2_MOUSE 1
+#define CONFIG_MOUSE 1
 // If the target machine has multiple independent root buses, the
 // extra buses may be specified here.
 #define CONFIG_PCI_ROOT1 0x00
@@ -75,7 +87,7 @@
 // Support finding and running option roms during post.
 #define CONFIG_OPTIONROMS 1
 // Set if option roms are already copied to 0xc0000-0xf0000
-#define CONFIG_OPTIONROMS_DEPLOYED 1
+#define CONFIG_OPTIONROMS_DEPLOYED 0
 // When option roms are not pre-deployed, SeaBIOS can copy an optionrom
 // from flash for up to 2 devices.
 #define OPTIONROM_VENDEV_1 0x00000000
@@ -120,14 +132,17 @@
 #define CONFIG_BIOS_REVISION 0x01
 
 // Various memory addresses used by the code.
-#define BUILD_STACK_ADDR          0x7c00
+#define BUILD_STACK_ADDR          0x7000
 #define BUILD_S3RESUME_STACK_ADDR 0x1000
 #define BUILD_AP_BOOT_ADDR        0x10000
+#define BUILD_EBDA_MINIMUM        0x90000
+#define BUILD_LOWRAM_END          0xa0000
 #define BUILD_ROM_START           0xc0000
 #define BUILD_BIOS_ADDR           0xf0000
 #define BUILD_BIOS_SIZE           0x10000
 // 32KB for shadow ram copying (works around emulator deficiencies)
 #define BUILD_BIOS_TMP_ADDR       0x30000
+#define BUILD_MAX_HIGHMEM         0xe0000000
 
 #define BUILD_APIC_ADDR           0xfee00000
 #define BUILD_IOAPIC_ADDR         0xfec00000
@@ -158,13 +173,13 @@
 #define DEBUG_ISR_09 9
 #define DEBUG_ISR_0e 9
 #define DEBUG_HDL_10 20
-#define DEBUG_HDL_11 1
-#define DEBUG_HDL_12 1
+#define DEBUG_HDL_11 2
+#define DEBUG_HDL_12 2
 #define DEBUG_HDL_13 10
-#define DEBUG_HDL_14 1
+#define DEBUG_HDL_14 2
 #define DEBUG_HDL_15 9
 #define DEBUG_HDL_16 9
-#define DEBUG_HDL_17 1
+#define DEBUG_HDL_17 2
 #define DEBUG_HDL_18 1
 #define DEBUG_HDL_19 1
 #define DEBUG_HDL_1a 9
@@ -177,5 +192,10 @@
 #define DEBUG_ISR_hwpic2 5
 #define DEBUG_HDL_pnp 1
 #define DEBUG_HDL_pmm 1
+#define DEBUG_HDL_pcibios32 9
+
+#define DEBUG_unimplemented 2
+#define DEBUG_invalid 3
+#define DEBUG_thread 2
 
 #endif // config.h