#######################################################
#
-# Main options file for LinuxBIOS
+# Main options file for coreboot
#
# Each option used by a part must be defined in
# this file. The format for options is:
export always
comment "Objcopy command"
end
-define LINUXBIOS_VERSION
+define COREBOOT_VERSION
default "2.0.0"
export always
format "\"%s\""
- comment "LinuxBIOS version"
+ comment "coreboot version"
end
-define LINUXBIOS_EXTRA_VERSION
+define COREBOOT_EXTRA_VERSION
default ""
export used
format "\"%s\""
- comment "LinuxBIOS extra version"
+ comment "coreboot extra version"
end
-define LINUXBIOS_BUILD
+define COREBOOT_BUILD
default "$(shell date)"
export always
format "\"%s\""
comment "Build date"
end
-define LINUXBIOS_COMPILE_TIME
+define COREBOOT_COMPILE_TIME
default "$(shell date +%T)"
export always
format "\"%s\""
comment "Build time"
end
-define LINUXBIOS_COMPILE_BY
+define COREBOOT_COMPILE_BY
default "$(shell whoami)"
export always
format "\"%s\""
comment "Who build this image"
end
-define LINUXBIOS_COMPILE_HOST
+define COREBOOT_COMPILE_HOST
default "$(shell hostname)"
export always
format "\"%s\""
comment "Build host"
end
-define LINUXBIOS_COMPILE_DOMAIN
+define COREBOOT_COMPILE_DOMAIN
default "$(shell dnsdomainname)"
export always
format "\"%s\""
comment "Build domain name"
end
-define LINUXBIOS_COMPILER
+define COREBOOT_COMPILER
default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
export always
format "\"%s\""
comment "Build compiler"
end
-define LINUXBIOS_LINKER
+define COREBOOT_LINKER
default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
export always
format "\"%s\""
comment "Build linker"
end
-define LINUXBIOS_ASSEMBLER
+define COREBOOT_ASSEMBLER
default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
export always
format "\"%s\""
export always
comment "Set if fallback booting required"
end
+define HAVE_FAILOVER_BOOT
+ format "%d"
+ default 0
+ export always
+ comment "Set if failover booting required"
+end
define USE_FALLBACK_IMAGE
format "%d"
default 0
export used
comment "Set to build a fallback image"
end
+define USE_FAILOVER_IMAGE
+ format "%d"
+ default 0
+ export used
+ comment "Set to build a failover image"
+end
define FALLBACK_SIZE
default 65536
format "0x%x"
export used
comment "Default fallback image size"
end
+define FAILOVER_SIZE
+ default 0
+ format "0x%x"
+ export used
+ comment "Default failover image size"
+end
define ROM_SIZE
default none
format "0x%x"
default {PAYLOAD_SIZE}
format "0x%x"
export always
- comment "Base address of LinuxBIOS in ROM"
+ comment "Base address of coreboot in ROM"
end
define _ROMSTART
default none
format "0x%x"
export used
- comment "Start address of LinuxBIOS in ROM"
+ comment "Start address of coreboot in ROM"
end
define _RESET
default {_ROMBASE}
default none
format "0x%x"
export always
- comment "Base address of LinuxBIOS in RAM"
+ comment "Base address of coreboot in RAM"
end
define _RAMSTART
default none
format "0x%x"
export used
- comment "Start address of LinuxBIOS in RAM"
+ comment "Start address of coreboot in RAM"
end
define USE_DCACHE_RAM
default 0
export always
comment "Use data cache as temporary RAM if possible"
end
+define CAR_FAM10
+ default 0
+ export always
+ comment "AMD family 10 CAR requires additional setup"
+end
define DCACHE_RAM_BASE
- default none
+ default 0xc0000
format "0x%x"
- export used
+ export always
comment "Base address of data cache when using it for temporary RAM"
end
define DCACHE_RAM_SIZE
export always
comment "Size of region that for global variable of cache as ram stage"
end
+define CONFIG_AP_CODE_IN_CAR
+ default 0
+ export always
+ comment "will copy coreboot_apc to AP cache ane execute in AP"
+end
+define MEM_TRAIN_SEQ
+ default 0
+ export always
+ comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
+end
+define WAIT_BEFORE_CPUS_INIT
+ default 0
+ export always
+ comment "execute cpus_ready_for_init if it is set to 1"
+end
define XIP_ROM_BASE
default 0
format "0x%x"
export used
- comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
+ comment "Start address of area to cache during coreboot execution directly from ROM"
end
define XIP_ROM_SIZE
default 0
format "0x%x"
export used
- comment "Size of area to cache during LinuxBIOS execution directly from ROM"
+ comment "Size of area to cache during coreboot execution directly from ROM"
end
define CONFIG_COMPRESS
default 1
default 49
format "%d"
export always
- comment "First CMOS byte to use for LinuxBIOS options"
+ comment "First CMOS byte to use for coreboot options"
end
define LB_CKS_RANGE_END
default 125
format "%d"
export always
- comment "Last CMOS byte to use for LinuxBIOS options"
+ comment "Last CMOS byte to use for coreboot options"
end
define LB_CKS_LOC
default 126
define CONFIG_CONSOLE_VGA
default 0
export always
- comment "Log messages to VGA"
+ comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
end
define CONFIG_CONSOLE_VGA_MULTI
default 0
export always
comment "Log messages to 8250 uart based serial console"
end
+define CONFIG_USBDEBUG_DIRECT
+ default 0
+ export always
+ comment "Log messages to ehci debug port console"
+end
define DEFAULT_CONSOLE_LOGLEVEL
default 7
export always
export always
comment "Default flow control settings for the 8250 serial console uart"
end
+
+define CONFIG_USE_PRINTK_IN_CAR
+ default 0
+ export always
+ comment "use printk instead of print in CAR stage code"
+end
+
###############################################
# Mainboard options
# Boot options
###############################################
-define CONFIG_IDE_STREAM
+define CONFIG_IDE_PAYLOAD
default 0
export always
comment "Boot from IDE device"
end
-define CONFIG_ROM_STREAM
+define CONFIG_ROM_PAYLOAD
default 0
export always
comment "Boot image is located in ROM"
end
-define CONFIG_ROM_STREAM_START
+define CONFIG_ROM_PAYLOAD_START
default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
format "0x%x"
export always
comment "ROM stream start location"
end
-define CONFIG_COMPRESSED_ROM_STREAM
+define CONFIG_COMPRESSED_PAYLOAD_NRV2B
+ default 0
+ export always
+ comment "NRV2B compressed boot image is located in ROM"
+end
+define CONFIG_COMPRESSED_PAYLOAD_LZMA
default 0
export always
- comment "compressed boot image is located in ROM"
+ comment "LZMA compressed boot image is located in ROM"
end
-define CONFIG_PRECOMPRESSED_ROM_STREAM
+define CONFIG_PRECOMPRESSED_PAYLOAD
default 0
export always
comment "boot image is already compressed"
end
-define CONFIG_FS_STREAM
+define CONFIG_SERIAL_PAYLOAD
+ default 0
+ export always
+ comment "Download boot image from serial port"
+end
+define CONFIG_FS_PAYLOAD
default 0
export always
comment "Boot from a filesystem"
export used
comment "Define if we have a PIRQ table"
end
+define PIRQ_ROUTE
+ default 0
+ export used
+ comment "Define if we have a PIRQ table and want routing IRQs"
+end
define IRQ_SLOT_COUNT
default none
export used
# Options for memory mapped I/O
###############################################
+define PCI_IO_CFG_EXT
+ default 0
+ export always
+ comment "allow 4K register space via io CFG port"
+end
+
define PCIC0_CFGADDR
default none
format "0x%x"
# Misc device options
###############################################
+define HAVE_FANCTL
+ default 0
+ export used
+ comment "Include board specific FAN control initialization"
+end
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
default 0
export used
define HT_CHAIN_UNITID_BASE
default 1
export always
- comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
+ comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
end
define HT_CHAIN_END_UNITID_BASE
comment "this will decided if only offset SB hypertransport chain"
end
-define K8_SB_HT_CHAIN_ON_BUS0
+define SB_HT_CHAIN_ON_BUS0
default 0
export always
- comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
+ comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
end
-define K8_HW_MEM_HOLE_SIZEK
+define PCI_BUS_SEGN_BITS
+ default 0
+ export always
+ comment "It could be 0, 1, 2, 3 and 4 only"
+end
+
+define MMCONF_SUPPORT
+ default 0
+ export always
+ comment "enable mmconfig for pci conf"
+end
+
+define MMCONF_SUPPORT_DEFAULT
+ default 0
+ export always
+ comment "enable mmconfig for pci conf"
+end
+
+define HW_MEM_HOLE_SIZEK
default 0
export always
comment "Opteron E0 later memory hole size in K, 0 mean disable"
end
-define K8_HW_MEM_HOLE_SIZE_AUTO_INC
+define HW_MEM_HOLE_SIZE_AUTO_INC
default 0
export always
comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
end
+define CONFIG_VAR_MTRR_HOLE
+ default 1
+ export always
+ comment "using hole in MTRR instead of increasing method"
+end
+
define K8_HT_FREQ_1G_SUPPORT
- default 0
+ default 0
export always
comment "Optern E0 later could support 1G HT, but still depends MB design"
end
+define K8_REV_F_SUPPORT
+ default 0
+ export always
+ comment "Opteron Rev F (DDR2) support"
+end
+
+define CBB
+ default 0
+ export always
+ comment "Opteron cpu bus num base"
+end
+
+define CDB
+ default 0x18
+ export always
+ comment "Opteron cpu device num base"
+end
+
+define HT3_SUPPORT
+ default 0
+ export always
+ comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
+end
+
+define EXT_RT_TBL_SUPPORT
+ default 0
+ export always
+ comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
+end
+
+define EXT_CONF_SUPPORT
+ default 0
+ export always
+ comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
+end
+
+define DIMM_SUPPORT
+ default 0x0108
+ format "0x%x"
+ export always
+ comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
+end
+
+define CPU_SOCKET_TYPE
+ default 0x10
+ export always
+ comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
+end
+
+define CPU_ADDR_BITS
+ default 36
+ export always
+ comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
+end
+
+define CONFIG_VGA_ROM_RUN
+ default 0
+ export always
+ comment "Init x86 ROMs on VGA-class PCI devices"
+end
+
define CONFIG_PCI_ROM_RUN
default 0
export always
- comment "Init PCI device option rom"
+ comment "Init x86 ROMs on all PCI devices"
end
define CONFIG_PCI_64BIT_PREF_MEM
comment "allow PCI device get 4G above Region as pref mem"
end
+define CONFIG_AMDMCT
+ default 0
+ export always
+ comment "use AMD MCT to init RAM instead of native code"
+end
+
+define AMD_UCODE_PATCH_FILE
+ default none
+ export used
+ format "\"%s\""
+ comment "name of the micorcode patch file"
+
+define CONFIG_VIDEO_MB
+ default none
+ export used
+ comment "Integrated graphics with UMA has dynamic setup"
+end
+
+define CONFIG_SPLASH_GRAPHIC
+ default 0
+ export used
+ comment "Paint a splash screen"
+end
+
+define CONFIG_GX1_VIDEO
+ default 0
+ export used
+ comment "Build in GX1's graphic support"
+end
+
+define CONFIG_GX1_VIDEOMODE
+ default none
+ export used
+ comment "Define video mode after reset"
+# could be
+# 0 for 640x480
+# 1 for 800x600
+# 2 for 1024x768
+# 3 for 1280x960
+# 4 for 1280x1024
+end
###############################################
# Board specific options
projects / coreboot.git / blobdiff