export always
comment "Default architecture is i386, options are alpha and ppc"
end
-define k7
- default none
- export always
- comment "We're a k7"
-end
-define k8
- default none
- export always
- comment "We're a k8"
-end
-define i586
- default none
- export always
- comment "We're a 586"
-end
-define i686
- default none
- export always
- comment "We're a 686"
-end
-define CPU_FIXUP
- default none
+define HAVE_MOVNTI
+ default 0
export always
- comment "Do CPU fixups"
+ comment "This cpu supports the MOVNTI directive"
end
###############################################
export always
comment "Host C Compiler"
end
+define CPU_OPT
+ default none
+ export used
+ comment "Additional per-cpu CFLAGS"
+end
define OBJCOPY
- default "$(CROSS_COMPILE)objcopy"
+ default "$(CROSS_COMPILE)objcopy --gap-fill 0xff"
export always
comment "Objcopy command"
end
define LINUXBIOS_VERSION
- default "1.1.0"
+ default "2.0.0"
export always
+ format "\"%s\""
comment "LinuxBIOS version"
end
+define LINUXBIOS_EXTRA_VERSION
+ default ""
+ export used
+ format "\"%s\""
+ comment "LinuxBIOS extra version"
+end
define LINUXBIOS_BUILD
default "$(shell date)"
export always
+ format "\"%s\""
comment "Build date"
end
define LINUXBIOS_COMPILE_TIME
default "$(shell date +%T)"
export always
+ format "\"%s\""
comment "Build time"
end
define LINUXBIOS_COMPILE_BY
default "$(shell whoami)"
export always
+ format "\"%s\""
comment "Who build this image"
end
define LINUXBIOS_COMPILE_HOST
default "$(shell hostname)"
export always
+ format "\"%s\""
comment "Build host"
end
define LINUXBIOS_COMPILE_DOMAIN
- default ""
+ default "$(shell dnsdomainname)"
export always
+ format "\"%s\""
comment "Build domain name"
end
define LINUXBIOS_COMPILER
default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -n 1)"
export always
+ format "\"%s\""
comment "Build compiler"
end
define LINUXBIOS_LINKER
- default "$(shell $(CC) -Wl,-v 2>&1 | grep version | tail -n 1)"
+ default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
export always
+ format "\"%s\""
comment "Build linker"
end
define LINUXBIOS_ASSEMBLER
default "$(shell touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
export always
+ format "\"%s\""
comment "Build assembler"
end
+define CONFIG_CHIP_CONFIGURE
+ default 0
+ export used
+ comment "Use new chip_configure method for configuring (non-pci) devices"
+end
+define CONFIG_USE_INIT
+ default 0
+ export always
+ comment "Use stage 1 initialization code"
+end
###############################################
# ROM image options
###############################################
define HAVE_FALLBACK_BOOT
+ format "%d"
default 0
export always
comment "Set if fallback booting required"
end
define USE_FALLBACK_IMAGE
+ format "%d"
default 0
export used
comment "Set to build a fallback image"
end
-define USE_NORMAL_IMAGE
- default {!USE_FALLBACK_IMAGE}
- export used
- comment "Set to build a normal image"
-end
define FALLBACK_SIZE
default 65536
format "0x%x"
comment "Default fallback image size"
end
define ROM_SIZE
- default 262144
+ default none
format "0x%x"
export used
comment "Size of your ROM"
default {PAYLOAD_SIZE}
format "0x%x"
export always
- comment "Base of ROM"
+ comment "Base address of LinuxBIOS in ROM"
+end
+define _ROMSTART
+ default none
+ format "0x%x"
+ export used
+ comment "Start address of LinuxBIOS in ROM"
+end
+define _RESET
+ default {_ROMBASE}
+ format "0x%x"
+ export always
+ comment "Hardware reset vector address"
+end
+define _EXCEPTION_VECTORS
+ default {_ROMBASE+0x100}
+ format "0x%x"
+ export always
+ comment "Address of exception vector table"
end
define STACK_SIZE
default 0x2000
define HEAP_SIZE
default 0x2000
format "0x%x"
- export used
+ export always
comment "Default heap size"
end
define _RAMBASE
- default 0x00100000
+ default none
format "0x%x"
export always
- comment "Base address of RAM"
+ comment "Base address of LinuxBIOS in RAM"
+end
+define _RAMSTART
+ default none
+ format "0x%x"
+ export used
+ comment "Start address of LinuxBIOS in RAM"
end
-define USE_CACHE_RAM
+define USE_DCACHE_RAM
default 0
+ export always
+ comment "Use data cache as temporary RAM if possible"
+end
+define DCACHE_RAM_BASE
+ default none
+ format "0x%x"
export used
- comment "Use cache as temporary RAM if possible"
+ comment "Base address of data cache when using it for temporary RAM"
end
-define CACHE_RAM_BASE
- default 0x00200000
+define DCACHE_RAM_SIZE
+ default 0x1000
format "0x%x"
export always
- comment "Base address of cache when using it for temporary RAM"
+ comment "Size of data cache when using it for temporary RAM"
end
-define CACHE_RAM_SIZE
- default 0x00004000
+define DCACHE_RAM_GLOBAL_VAR_SIZE
+ default 0
format "0x%x"
export always
- comment "Size of cache when using it for temporary RAM"
+ comment "Size of region that for global variable of cache as ram stage"
+end
+define XIP_ROM_BASE
+ default 0
+ format "0x%x"
+ export used
+ comment "Start address of area to cache during LinuxBIOS execution directly from ROM"
+end
+define XIP_ROM_SIZE
+ default 0
+ format "0x%x"
+ export used
+ comment "Size of area to cache during LinuxBIOS execution directly from ROM"
end
define CONFIG_COMPRESS
default 1
comment "Set for compressed image"
end
define CONFIG_UNCOMPRESSED
+ format "%d"
default {!CONFIG_COMPRESS}
export always
comment "Set for uncompressed image"
end
+define CONFIG_LB_MEM_TOPK
+ format "%d"
+ default 2048
+ export always
+ comment "Kilobytes of memory to initialized before executing code from RAM"
+end
define HAVE_OPTION_TABLE
default 0
export always
comment "Export CMOS option table"
end
define USE_OPTION_TABLE
+ format "%d"
default {HAVE_OPTION_TABLE && !USE_FALLBACK_IMAGE}
export always
comment "Use option table"
end
+###############################################
+# CMOS variable options
+###############################################
+define LB_CKS_RANGE_START
+ default 49
+ format "%d"
+ export always
+ comment "First CMOS byte to use for LinuxBIOS options"
+end
+define LB_CKS_RANGE_END
+ default 125
+ format "%d"
+ export always
+ comment "Last CMOS byte to use for LinuxBIOS options"
+end
+define LB_CKS_LOC
+ default 126
+ format "%d"
+ export always
+ comment "Pair of bytes to use for CMOS checksum"
+end
+
+
###############################################
# Build targets
###############################################
define CRT0
- default "$(TOP)/src/arch/$(ARCH)/config/crt0.base"
+ default "$(TOP)/src/arch/$(ARCH)/init/crt0.S.lb"
export always
comment "Main initialization target"
end
export always
comment "Log messages to VGA"
end
+define CONFIG_CONSOLE_VGA_MULTI
+ default 0
+ export always
+ comment "Multi VGA console"
+end
+define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
+ default 0
+ export always
+ comment "Use onboard VGA instead of add on VGA card"
+end
+define CONFIG_CONSOLE_BTEXT
+ default 0
+ export always
+ comment "Log messages to btext fb console"
+end
define CONFIG_CONSOLE_LOGBUF
default 0
export always
define CONFIG_CONSOLE_SERIAL8250
default 0
export always
- comment "Log messages to serial 8250 console"
+ comment "Log messages to 8250 uart based serial console"
end
-define SERIAL_CONSOLE
- default none
- export used
- comment "Log messages to serial console"
+define DEFAULT_CONSOLE_LOGLEVEL
+ default 7
+ export always
+ comment "Console will log at this level unless changed"
end
define MAXIMUM_CONSOLE_LOGLEVEL
- default 7
+ default 8
+ export always
+ comment "Error messages up to this level can be printed"
+end
+define CONFIG_SERIAL_POST
+ default 0
export always
- comment "Console will log at this level"
+ comment "Enable SERIAL POST codes"
end
define NO_POST
default none
- export always
+ export used
comment "Disable POST codes"
end
+define TTYS0_BASE
+ default 0x3f8
+ format "0x%x"
+ export always
+ comment "Base address for 8250 uart for the serial console"
+end
define TTYS0_BAUD
default 115200
export always
comment "Default baud rate for serial console"
end
-define NO_KEYBOARD
+define TTYS0_DIV
default none
- export never
- comment "Set if we don't have a keyboard"
+ format "%d"
+ export used
+ comment "Allow UART divisor to be set explicitly"
end
-
+define TTYS0_LCS
+ default 0x3
+ format "0x%x"
+ export always
+ comment "Default flow control settings for the 8250 serial console uart"
+end
+
###############################################
# Mainboard options
###############################################
define MAINBOARD_PART_NUMBER
default "Part_number_not_set"
export always
+ format "\"%s\""
comment "Part number of mainboard"
end
define MAINBOARD_VENDOR
default "Vendor_not_set"
export always
+ format "\"%s\""
comment "Vendor of mainboard"
end
-define FINAL_MAINBOARD_FIXUP
+define MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ default 0
+ export always
+ comment "PCI Vendor ID of mainboard manufacturer"
+end
+define MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
default 0
+ format "0x%x"
+ export always
+ comment "PCI susbsystem device id assigned my mainboard manufacturer"
+end
+define MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+ default none
export used
- comment "Do final mainboard fixups"
+ comment "Default power on after power fail setting"
+end
+define CONFIG_SYS_CLK_FREQ
+ default none
+ export used
+ comment "System clock frequency in MHz"
+end
+define CONFIG_MAX_PCI_BUSES
+ default 255
+ export always
+ comment "Maximum number of PCI buses to search for devices"
end
-
-
###############################################
# SMP options
###############################################
export always
comment "Define if we support SMP"
end
-define SMP
- default none
- export always
- comment "Define if we support SMP"
+define CONFIG_MAX_CPUS
+ default 1
+ export always
+ comment "Maximum CPU count for this machine"
end
-define MAX_CPUS
- default 1
- export always
- comment "CPU count for this machine"
+define CONFIG_MAX_PHYSICAL_CPUS
+ default 1
+ export always
+ comment "Maximum physical CPU count for this machine"
end
define CONFIG_LOGICAL_CPUS
- default 1
- export always
- comment "Logical CPU count for this machine"
-end
-define MAX_PHYSICAL_CPUS
- default 1
+ default 0
export always
- comment "Physical CPU count for this machine"
+ comment "Should multiple cpus per die be enabled?"
end
define HAVE_MP_TABLE
default none
- export always
+ export used
comment "Define to build an MP table"
end
-
+define SERIAL_CPU_INIT
+ default 1
+ export always
+ comment "Serialize CPU init"
+end
+define APIC_ID_OFFSET
+ default 0
+ export always
+ comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
+end
+define ENABLE_APIC_EXT_ID
+ default 0
+ export always
+ comment "Enable APIC ext id mode 8 bit"
+end
+define LIFT_BSP_APIC_ID
+ default 0
+ export always
+ comment "decide if we lift bsp apic id while ap apic id"
+end
###############################################
# Boot options
###############################################
-define USE_ELF_BOOT
- default none
- export always
- comment "Use ELF boot loader"
-end
define CONFIG_IDE_STREAM
default 0
export always
export always
comment "ROM stream start location"
end
+define CONFIG_COMPRESSED_ROM_STREAM
+ default 0
+ export always
+ comment "compressed boot image is located in ROM"
+end
+define CONFIG_PRECOMPRESSED_ROM_STREAM
+ default 0
+ export always
+ comment "boot image is already compressed"
+end
+define CONFIG_FS_STREAM
+ default 0
+ export always
+ comment "Boot from a filesystem"
+end
+define CONFIG_FS_EXT2
+ default 0
+ export always
+ comment "Enable ext2 filesystem support"
+end
+define CONFIG_FS_ISO9660
+ default 0
+ export always
+ comment "Enable ISO9660 filesystem support"
+end
+define CONFIG_FS_FAT
+ default 0
+ export always
+ comment "Enable FAT filesystem support"
+end
+define AUTOBOOT_DELAY
+ default 2
+ export always
+ comment "Delay (in seconds) before autobooting"
+end
+define AUTOBOOT_CMDLINE
+ default "hdc1:/vmlinuz root=/dev/hdc3 console=tty0 console=ttyS0,115200"
+ export always
+ format "\"%s\""
+ comment "Default command line when autobooting"
+end
+
+define USE_WATCHDOG_ON_BOOT
+ default 0
+ export always
+ comment "Use the watchdog on booting"
+end
+
+###############################################
+# Plugin Device support options
+###############################################
+
+define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
+ default 1
+ export always
+ comment "Enable support for plugin Hypertransport busses"
+end
+define CONFIG_AGP_PLUGIN_SUPPORT
+ default 1
+ export always
+ comment "Enable support for plugin AGP busses"
+end
+define CONFIG_CARDBUS_PLUGIN_SUPPORT
+ default 1
+ export always
+ comment "Enable support cardbus plugin cards"
+end
+define CONFIG_PCIX_PLUGIN_SUPPORT
+ default 1
+ export always
+ comment "Enable support for plugin PCI-X busses"
+end
+define CONFIG_PCIEXP_PLUGIN_SUPPORT
+ default 1
+ export always
+ comment "Enable support for plugin PCI-E busses"
+end
###############################################
# IRQ options
define HAVE_PIRQ_TABLE
default none
- export always
+ export used
comment "Define if we have a PIRQ table"
end
define IRQ_SLOT_COUNT
default none
- export always
+ export used
comment "Number of IRQ slots"
end
define CONFIG_PCIBIOS_IRQ
default none
- export always
+ export used
comment "PCIBIOS IRQ support"
end
define CONFIG_IOAPIC
default none
- export always
+ export used
comment "IOAPIC support"
end
# IDE specific options
###############################################
+define CONFIG_IDE
+ default 0
+ export always
+ comment "Define to include IDE support"
+end
define IDE_BOOT_DRIVE
default 0
export always
end
define IDE_SWAB
default none
- export always
+ export used
comment "Swap bytes when reading from IDE device"
end
define IDE_OFFSET
end
###############################################
-# SMBUS options
+# Options for memory mapped I/O
###############################################
-define SMBUS_MEM_DEVICE_START
- default (0xa << 3)
- export always
- comment "Start address of SMBUS device"
+define PCIC0_CFGADDR
+ default none
+ format "0x%x"
+ export used
+ comment "Address of PCI Configuration Address Register"
end
-define SMBUS_MEM_DEVICE_END
- default {SMBUS_MEM_DEVICE_START +1}
- export always
- comment "End address of SMBUS device"
+define PCIC0_CFGDATA
+ default none
+ format "0x%x"
+ export used
+ comment "Address of PCI Configuration Data Register"
end
-define SMBUS_MEM_DEVICE_INC
- default 1
- export always
- comment "Increment value SMBUS"
+define ISA_IO_BASE
+ default none
+ format "0x%x"
+ export used
+ comment "Base address of PCI/ISA I/O address range"
+end
+define ISA_MEM_BASE
+ default none
+ format "0x%x"
+ export used
+ comment "Base address of PCI/ISA memory address range"
+end
+define PNP_CFGADDR
+ default none
+ format "0x%x"
+ export used
+ comment "PNP Configuration Address Register offset"
+end
+define PNP_CFGDATA
+ default none
+ format "0x%x"
+ export used
+ comment "PNP Configuration Data Register offset"
+end
+define _IO_BASE
+ default none
+ format "0x%x"
+ export used
+ comment "Base address of memory mapped I/O operations"
end
###############################################
-# SuperIO options
+# Options for embedded systems
###############################################
-define SIO_BASE
+define EMBEDDED_RAM_SIZE
default none
export used
- comment "Superio base address"
-end
-define SIO_SYSTEM_CLK_INPUT
- default none
- export used
- comment "Superio CLK input default"
+ comment "Embedded boards generally have fixed RAM size"
end
###############################################
# Misc options
###############################################
+define CONFIG_CHIP_NAME
+ default 0
+ export always
+ comment "Compile in the chip name"
+end
+
+define CONFIG_GDB_STUB
+ default 0
+ export used
+ comment "Compile in gdb stub support?"
+end
+
+define HAVE_INIT_TIMER
+ default 0
+ export always
+ comment "Have a init_timer function"
+end
define HAVE_HARD_RESET
default none
export used
export used
comment "Set to deal with memory hole"
end
-define ENABLE_FIXED_AND_VARIABLE_MTRRS
- default none
- export used
- comment "Enable fixed and variable mtrrs"
-end
-define START_CPU_SEG
- default 0xf0000
- format "0x%x"
- export always
- comment "Start CPU segment"
-end
define MAX_REBOOT_CNT
- default 2
+ default 3
export always
comment "Set maximum reboots"
end
-define DISABLE_WATCHDOG
- default {MAXIMUM_CONSOLE_LOGLEVEL >= 8}
- export used
- comment "Disable watchdog if we're doing lots of output"
-end
###############################################
# Misc device options
###############################################
define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
- default none
+ default 0
export used
- comment ""
+ comment "Use timer2 to callibrate the x86 time stamp counter"
end
define INTEL_PPRO_MTRR
default none
- export always
- comment ""
-end
-define AMD8111_DEV
- default 0x3800
- format "0x%x"
export used
comment ""
end
define CONFIG_UDELAY_TSC
default 0
export used
- comment ""
+ comment "Implement udelay with the x86 time stamp counter"
+end
+define CONFIG_UDELAY_IO
+ default 0
+ export used
+ comment "Implement udelay with x86 io registers"
+end
+define FAKE_SPDROM
+ default 0
+ export always
+ comment "Use this to fake spd rom values"
+end
+
+define HAVE_ACPI_TABLES
+ default 0
+ export always
+ comment "Define to build ACPI tables"
+end
+
+define ACPI_SSDTX_NUM
+ default 0
+ export always
+ comment "extra ssdt num for PCI Device"
+end
+
+define AGP_APERTURE_SIZE
+ default none
+ export used
+ format "0x%x"
+ comment "AGP graphics virtual memory aperture size"
+end
+
+define HT_CHAIN_UNITID_BASE
+ default 1
+ export always
+ comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
+end
+
+define HT_CHAIN_END_UNITID_BASE
+ default 0x20
+ export always
+ comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
+end
+
+define SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ default 1
+ export always
+ comment "this will decided if only offset SB hypertransport chain"
+end
+
+define K8_SB_HT_CHAIN_ON_BUS0
+ default 0
+ export always
+ comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
+end
+
+define K8_HW_MEM_HOLE_SIZEK
+ default 0
+ export always
+ comment "Opteron E0 later memory hole size in K, 0 mean disable"
+end
+
+define K8_HW_MEM_HOLE_SIZE_AUTO_INC
+ default 0
+ export always
+ comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
+end
+
+define K8_HT_FREQ_1G_SUPPORT
+ default 0
+ export always
+ comment "Optern E0 later could support 1G HT, but still depends MB design"
+end
+
+define CONFIG_PCI_ROM_RUN
+ default 0
+ export always
+ comment "Init PCI device option rom"
end
+define CONFIG_PCI_64BIT_PREF_MEM
+ default 0
+ export always
+ comment "allow PCI device get 4G above Region as pref mem"
+end
+
+
###############################################
-# Board specifig options
+# Board specific options
###############################################
###############################################
export never
comment "Configure Sandpoint with Gyrus PMC"
end
+
+###############################################
+# Options for totalimpact/briq
+###############################################
+define CONFIG_BRIQ_750FX
+ default 0
+ export never
+ comment "Configure briQ with PowerPC 750FX"
+end
+define CONFIG_BRIQ_7400
+ default 0
+ export never
+ comment "Configure briQ with PowerPC G4"
+end
projects / coreboot.git / blobdiff