comment "Objcopy command"
end
define LINUXBIOS_VERSION
- default "1.1.8"
+ default "2.0.0"
export always
format "\"%s\""
comment "LinuxBIOS version"
comment "Build compiler"
end
define LINUXBIOS_LINKER
- default "$(shell $(CC) -Wl,-v 2>&1 | grep version | tail -n 1)"
+ default "$(shell $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
export always
format "\"%s\""
comment "Build linker"
default 65536
format "0x%x"
export used
- comment "ROM_SECTION_SIZE to use for the fallback build."
+ comment "Default fallback image size"
end
define ROM_SIZE
default none
format "0x%x"
export used
- comment "Total number of bytes allocated for normal and fallback LinuxBIOS images and payloads. Note that the fallback image goes at the end of the ROM, and the normal image at the beginning."
+ comment "Size of your ROM"
end
define ROM_IMAGE_SIZE
default 65535
format "0x%x"
export always
- comment "Maximum number of bytes allowed for a LinuxBIOS image. Does not include the payload."
+ comment "Default image size"
end
define ROM_SECTION_SIZE
default {FALLBACK_SIZE}
format "0x%x"
export used
- comment "Default rom section size. Normally, this is calculated in mainboard Config.lb and varies between the normal and fallback builds."
+ comment "Default rom section size"
end
define ROM_SECTION_OFFSET
default {ROM_SIZE - FALLBACK_SIZE}
format "0x%x"
export used
- comment "Number of bytes from the beginning of the ROM to the start of the section containing this build (normal or fallback). Normally, this is calculated in mainboard Config.lb."
+ comment "Default rom section offset"
end
define PAYLOAD_SIZE
default {ROM_SECTION_SIZE - ROM_IMAGE_SIZE}
format "0x%x"
export always
- comment "Maximum number of bytes allowed for a payload. Normally, this is calculated as above."
+ comment "Default payload size"
end
define _ROMBASE
default {PAYLOAD_SIZE}
comment "Base address of data cache when using it for temporary RAM"
end
define DCACHE_RAM_SIZE
- default none
+ default 0x1000
format "0x%x"
- export used
+ export always
comment "Size of data cache when using it for temporary RAM"
end
+define DCACHE_RAM_GLOBAL_VAR_SIZE
+ default 0
+ format "0x%x"
+ export always
+ comment "Size of region that for global variable of cache as ram stage"
+end
define XIP_ROM_BASE
default 0
format "0x%x"
end
define CONFIG_LB_MEM_TOPK
format "%d"
- default 1024
+ default 2048
export always
comment "Kilobytes of memory to initialized before executing code from RAM"
end
export always
comment "Log messages to VGA"
end
+define CONFIG_CONSOLE_VGA_MULTI
+ default 0
+ export always
+ comment "Multi VGA console"
+end
+define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
+ default 0
+ export always
+ comment "Use onboard VGA instead of add on VGA card"
+end
define CONFIG_CONSOLE_BTEXT
default 0
export always
export used
comment "System clock frequency in MHz"
end
-
+define CONFIG_MAX_PCI_BUSES
+ default 255
+ export always
+ comment "Maximum number of PCI buses to search for devices"
+end
###############################################
# SMP options
###############################################
export always
comment "Serialize CPU init"
end
-
+define APIC_ID_OFFSET
+ default 0
+ export always
+ comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
+end
+define ENABLE_APIC_EXT_ID
+ default 0
+ export always
+ comment "Enable APIC ext id mode 8 bit"
+end
+define LIFT_BSP_APIC_ID
+ default 0
+ export always
+ comment "decide if we lift bsp apic id while ap apic id"
+end
###############################################
# Boot options
###############################################
default {0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1}
format "0x%x"
export always
- comment "Memory address of this (normal or fallback) build's payload in ROM. Normally, this is calculated as above."
+ comment "ROM stream start location"
+end
+define CONFIG_COMPRESSED_ROM_STREAM
+ default 0
+ export always
+ comment "compressed boot image is located in ROM"
+end
+define CONFIG_PRECOMPRESSED_ROM_STREAM
+ default 0
+ export always
+ comment "boot image is already compressed"
end
define CONFIG_FS_STREAM
default 0
export used
comment "Implement udelay with the x86 time stamp counter"
end
+define CONFIG_UDELAY_IO
+ default 0
+ export used
+ comment "Implement udelay with x86 io registers"
+end
define FAKE_SPDROM
default 0
export always
comment "Define to build ACPI tables"
end
+define ACPI_SSDTX_NUM
+ default 0
+ export always
+ comment "extra ssdt num for PCI Device"
+end
+
define AGP_APERTURE_SIZE
default none
export used
comment "AGP graphics virtual memory aperture size"
end
-define CK804_DEVN_BASE
+define HT_CHAIN_UNITID_BASE
default 1
export always
- comment "CK804 device count from 0 or 1"
+ comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
+end
+
+define HT_CHAIN_END_UNITID_BASE
+ default 0x20
+ export always
+ comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than HT_CHAIN_UNITID_BASE, it could be 0"
+end
+
+define SB_HT_CHAIN_UNITID_OFFSET_ONLY
+ default 1
+ export always
+ comment "this will decided if only offset SB hypertransport chain"
end
-define K8_E0_MEM_HOLE_SIZEK
+define K8_SB_HT_CHAIN_ON_BUS0
+ default 0
+ export always
+ comment "this will make SB hypertransport chain sit on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
+end
+
+define K8_HW_MEM_HOLE_SIZEK
+ default 0
+ export always
+ comment "Opteron E0 later memory hole size in K, 0 mean disable"
+end
+
+define K8_HW_MEM_HOLE_SIZE_AUTO_INC
default 0
export always
- comment "Opteron E0 later memory hole size in K"
+ comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
+end
+
+define K8_HT_FREQ_1G_SUPPORT
+ default 0
+ export always
+ comment "Optern E0 later could support 1G HT, but still depends MB design"
end
define CONFIG_PCI_ROM_RUN
comment "Init PCI device option rom"
end
+define CONFIG_PCI_64BIT_PREF_MEM
+ default 0
+ export always
+ comment "allow PCI device get 4G above Region as pref mem"
+end
+
###############################################
# Board specific options
projects / coreboot.git / blobdiff