// 16bit code to handle system clocks.
//
-// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
+// Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2002 MandrakeSoft S.A.
//
-// This file may be distributed under the terms of the GNU GPLv3 license.
+// This file may be distributed under the terms of the GNU LGPLv3 license.
#include "biosvar.h" // SET_BDA
#include "util.h" // debug_enter
#include "pic.h" // eoi_pic1
#include "bregs.h" // struct bregs
#include "biosvar.h" // GET_GLOBAL
+#include "usb-hid.h" // usb_check_event
// RTC register flags
#define RTC_A_UIP 0x80
-#define RTC_B_SET 0x80
-#define RTC_B_PIE 0x40
-#define RTC_B_AIE 0x20
-#define RTC_B_UIE 0x10
+
+#define RTC_B_SET 0x80
+#define RTC_B_PIE 0x40
+#define RTC_B_AIE 0x20
+#define RTC_B_UIE 0x10
+#define RTC_B_BIN 0x04
+#define RTC_B_24HR 0x02
+#define RTC_B_DSE 0x01
+
// Bits for PORT_PS2_CTRLB
#define PPCB_T2GATE (1<<0)
* TSC timer
****************************************************************/
-#define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
-#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
+#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
-extern u32 cpu_khz;
-#if MODE16
-u32 cpu_khz VISIBLE16;
-#endif
+u32 cpu_khz VAR16VISIBLE;
static void
-calibrate_tsc()
+calibrate_tsc(void)
{
// Setup "timer2"
u8 orig = inb(PORT_PS2_CTRLB);
}
static void
-tscsleep(u64 diff)
+tscdelay(u64 diff)
{
u64 start = rdtscll();
u64 end = start + diff;
- while (rdtscll() < end)
+ while (!check_tsc(end))
cpu_relax();
}
-void
-ndelay(u32 count)
+static void
+tscsleep(u64 diff)
{
- u32 khz = GET_GLOBAL(cpu_khz);
- tscsleep(count * khz / 1000000);
+ u64 start = rdtscll();
+ u64 end = start + diff;
+ while (!check_tsc(end))
+ yield();
}
-void
-udelay(u32 count)
-{
- u32 khz = GET_GLOBAL(cpu_khz);
- tscsleep(count * khz / 1000);
+
+void ndelay(u32 count) {
+ tscdelay(count * GET_GLOBAL(cpu_khz) / 1000000);
}
-void
-mdelay(u32 count)
-{
- u32 khz = GET_GLOBAL(cpu_khz);
- tscsleep(count * khz);
+void udelay(u32 count) {
+ tscdelay(count * GET_GLOBAL(cpu_khz) / 1000);
+}
+void mdelay(u32 count) {
+ tscdelay(count * GET_GLOBAL(cpu_khz));
+}
+
+void nsleep(u32 count) {
+ tscsleep(count * GET_GLOBAL(cpu_khz) / 1000000);
+}
+void usleep(u32 count) {
+ tscsleep(count * GET_GLOBAL(cpu_khz) / 1000);
+}
+void msleep(u32 count) {
+ tscsleep(count * GET_GLOBAL(cpu_khz));
}
// Return the TSC value that is 'msecs' time in the future.
u32 khz = GET_GLOBAL(cpu_khz);
return rdtscll() + ((u64)khz * msecs);
}
+u64
+calc_future_tsc_usec(u32 usecs)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ return rdtscll() + ((u64)(khz/1000) * usecs);
+}
/****************************************************************
****************************************************************/
static int
-rtc_updating()
+rtc_updating(void)
{
// This function checks to see if the update-in-progress bit
// is set in CMOS Status Register A. If not, it returns 0.
// If it is set, it tries to wait until there is a transition
// to 0, and will return 0 if such a transition occurs. A -1
// is returned only after timing out. The maximum period
- // that this bit should be set is constrained to 244useconds, so
- // we wait for 1 msec max.
+ // that this bit should be set is constrained to (1984+244)
+ // useconds, but we wait for longer just to be sure.
- if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
return 0;
- u64 end = calc_future_tsc(1);
- do {
- if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ u64 end = calc_future_tsc(15);
+ for (;;) {
+ if ((inb_cmos(CMOS_STATUS_A) & RTC_A_UIP) == 0)
return 0;
- } while (rdtscll() <= end);
-
- // update-in-progress never transitioned to 0
- return -1;
+ if (check_tsc(end))
+ // update-in-progress never transitioned to 0
+ return -1;
+ yield();
+ }
}
static void
-pit_setup()
+pit_setup(void)
{
// timer0: binary count, 16bit count, mode 2
outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
outb(0x0, PORT_PIT_COUNTER0);
}
+static void
+init_rtc(void)
+{
+ outb_cmos(0x26, CMOS_STATUS_A); // 32,768Khz src, 976.5625us updates
+ u8 regB = inb_cmos(CMOS_STATUS_B);
+ outb_cmos((regB & RTC_B_DSE) | RTC_B_24HR, CMOS_STATUS_B);
+ inb_cmos(CMOS_STATUS_C);
+ inb_cmos(CMOS_STATUS_D);
+}
+
static u32
bcd2bin(u8 val)
{
}
void
-timer_setup()
+timer_setup(void)
{
dprintf(3, "init timer\n");
calibrate_tsc();
pit_setup();
+ init_rtc();
rtc_updating();
u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
- u32 ticks = (seconds * 18206507) / 1000000;
u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
- ticks += (minutes * 10923904) / 10000;
u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
- ticks += (hours * 65543427) / 1000;
+ u32 ticks = (hours * 60 + minutes) * 60 + seconds;
+ ticks = ((u64)ticks * PIT_TICK_RATE) / PIT_TICK_INTERVAL;
SET_BDA(timer_counter, ticks);
- SET_BDA(timer_rollover, 0);
- enable_hwirq(0, entry_08);
- enable_hwirq(8, entry_70);
-}
-
-static void
-init_rtc()
-{
- outb_cmos(0x26, CMOS_STATUS_A);
- outb_cmos(0x02, CMOS_STATUS_B);
- inb_cmos(CMOS_STATUS_C);
- inb_cmos(CMOS_STATUS_D);
+ enable_hwirq(0, FUNC16(entry_08));
+ enable_hwirq(8, FUNC16(entry_70));
}
* Standard clock functions
****************************************************************/
+#define TICKS_PER_DAY (u32)((u64)60*60*24*PIT_TICK_RATE / PIT_TICK_INTERVAL)
+
+// Calculate the timer value at 'count' number of full timer ticks in
+// the future.
+u32
+calc_future_timer_ticks(u32 count)
+{
+ return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
+}
+
+// Return the timer value that is 'msecs' time in the future.
+u32
+calc_future_timer(u32 msecs)
+{
+ if (!msecs)
+ return GET_BDA(timer_counter);
+ u32 kticks = DIV_ROUND_UP((u64)msecs * PIT_TICK_RATE, PIT_TICK_INTERVAL);
+ u32 ticks = DIV_ROUND_UP(kticks, 1000);
+ return calc_future_timer_ticks(ticks);
+}
+
+// Check if the given timer value has passed.
+int
+check_timer(u32 end)
+{
+ return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
+ < (TICKS_PER_DAY/2));
+}
+
// get current clock count
static void
handle_1a00(struct bregs *regs)
{
+ yield();
u32 ticks = GET_BDA(timer_counter);
regs->cx = ticks >> 16;
regs->dx = ticks;
handle_1a02(struct bregs *regs)
{
if (rtc_updating()) {
- set_fail(regs);
+ set_invalid(regs);
return;
}
regs->dh = inb_cmos(CMOS_RTC_SECONDS);
regs->cl = inb_cmos(CMOS_RTC_MINUTES);
regs->ch = inb_cmos(CMOS_RTC_HOURS);
- regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
+ regs->dl = inb_cmos(CMOS_STATUS_B) & RTC_B_DSE;
regs->ah = 0;
regs->al = regs->ch;
set_success(regs);
outb_cmos(regs->cl, CMOS_RTC_MINUTES);
outb_cmos(regs->ch, CMOS_RTC_HOURS);
// Set Daylight Savings time enabled bit to requested value
- u8 val8 = (inb_cmos(CMOS_STATUS_B) & 0x60) | 0x02 | (regs->dl & 0x01);
+ u8 val8 = ((inb_cmos(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
+ | RTC_B_24HR | (regs->dl & RTC_B_DSE));
outb_cmos(val8, CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // val last written to Reg B
{
regs->ah = 0;
if (rtc_updating()) {
- set_fail(regs);
+ set_invalid(regs);
return;
}
regs->cl = inb_cmos(CMOS_RTC_YEAR);
regs->dh = inb_cmos(CMOS_RTC_MONTH);
regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
- regs->ch = inb_cmos(CMOS_CENTURY);
+ if (CONFIG_COREBOOT) {
+ if (regs->cl > 0x80)
+ regs->ch = 0x19;
+ else
+ regs->ch = 0x20;
+ } else {
+ regs->ch = inb_cmos(CMOS_CENTURY);
+ }
regs->al = regs->ch;
set_success(regs);
}
// My assumption: RegB = (RegB & 01111111b)
if (rtc_updating()) {
init_rtc();
- set_fail(regs);
+ set_invalid(regs);
return;
}
outb_cmos(regs->cl, CMOS_RTC_YEAR);
outb_cmos(regs->dh, CMOS_RTC_MONTH);
outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
- outb_cmos(regs->ch, CMOS_CENTURY);
+ if (!CONFIG_COREBOOT)
+ outb_cmos(regs->ch, CMOS_CENTURY);
// clear halt-clock bit
u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
outb_cmos(val8, CMOS_STATUS_B);
// My assumption: RegB = ((RegB & 01111111b) | 00100000b)
u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
regs->ax = 0;
- if (val8 & 0x20) {
+ if (val8 & RTC_B_AIE) {
// Alarm interrupt enabled already
- set_fail(regs);
+ set_invalid(regs);
return;
}
if (rtc_updating()) {
static void
handle_1aXX(struct bregs *regs)
{
- set_fail(regs);
+ set_unimplemented(regs);
}
// INT 1Ah Time-of-day Service Entry Point
}
}
-// User Timer Tick
-void VISIBLE16
-handle_1c()
-{
- debug_isr(DEBUG_ISR_1c);
-}
-
// INT 08h System Timer ISR Entry Point
void VISIBLE16
-handle_08()
+handle_08(void)
{
debug_isr(DEBUG_ISR_08);
- irq_enable();
floppy_tick();
u32 counter = GET_BDA(timer_counter);
counter++;
// compare to one days worth of timer ticks at 18.2 hz
- if (counter >= 0x001800B0) {
+ if (counter >= TICKS_PER_DAY) {
// there has been a midnight rollover at this point
counter = 0;
SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
SET_BDA(timer_counter, counter);
- // chain to user timer tick INT #0x1c
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x1c, &br);
+ usb_check_event();
- irq_disable();
+ // chain to user timer tick INT #0x1c
+ u32 eax=0, flags;
+ call16_simpint(0x1c, &eax, &flags);
eoi_pic1();
}
* Periodic timer
****************************************************************/
+void
+useRTC(void)
+{
+ u16 ebda_seg = get_ebda_seg();
+ int count = GET_EBDA2(ebda_seg, RTCusers);
+ SET_EBDA2(ebda_seg, RTCusers, count+1);
+ if (count)
+ return;
+ // Turn on the Periodic Interrupt timer
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
+}
+
+void
+releaseRTC(void)
+{
+ u16 ebda_seg = get_ebda_seg();
+ int count = GET_EBDA2(ebda_seg, RTCusers);
+ SET_EBDA2(ebda_seg, RTCusers, count-1);
+ if (count != 1)
+ return;
+ // Clear the Periodic Interrupt.
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
+}
+
static int
set_usertimer(u32 usecs, u16 seg, u16 offset)
{
// Interval not already set.
SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
- SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
+ SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
SET_BDA(user_wait_timeout, usecs);
-
- // Turn on the Periodic Interrupt timer
- u8 bRegister = inb_cmos(CMOS_STATUS_B);
- outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
-
+ useRTC();
return 0;
}
static void
-clear_usertimer()
+clear_usertimer(void)
{
+ if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
+ return;
// Turn off status byte.
SET_BDA(rtc_wait_flag, 0);
- // Clear the Periodic Interrupt.
- u8 bRegister = inb_cmos(CMOS_STATUS_B);
- outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
+ releaseRTC();
}
#define RET_ECLOCKINUSE 0x83
u32 count = (regs->cx << 16) | regs->dx;
int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
if (ret) {
- set_code_fail(regs, RET_ECLOCKINUSE);
+ set_code_invalid(regs, RET_ECLOCKINUSE);
return;
}
- irq_enable();
while (!statusflag)
- cpu_relax();
- irq_disable();
+ wait_irq();
set_success(regs);
}
int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
if (ret)
// Interval already set.
- set_code_fail(regs, RET_EUNSUPPORTED);
+ set_code_invalid(regs, RET_EUNSUPPORTED);
else
set_success(regs);
}
static void
handle_1583XX(struct bregs *regs)
{
- set_code_fail(regs, RET_EUNSUPPORTED);
+ set_code_unimplemented(regs, RET_EUNSUPPORTED);
regs->al--;
}
}
}
+#define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
+
// int70h: IRQ8 - CMOS RTC
void VISIBLE16
-handle_70()
+handle_70(void)
{
debug_isr(DEBUG_ISR_70);
if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
goto done;
- if (registerC & 0x20) {
+ if (registerC & RTC_B_AIE) {
// Handle Alarm Interrupt.
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x4a, &br);
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x4a, &eax, &flags);
}
- if (!(registerC & 0x40))
+ if (!(registerC & RTC_B_PIE))
goto done;
// Handle Periodic Interrupt.
+ check_preempt();
+
if (!GET_BDA(rtc_wait_flag))
goto done;
// Wait Interval (Int 15, AH=83) active.
u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
- if (time < 0x3D1) {
+ if (time < USEC_PER_RTC) {
// Done waiting - write to specified flag byte.
- u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
- u16 segment = segoff >> 16;
- u16 offset = segoff & 0xffff;
- u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
- SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
+ struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
+ u16 ptr_seg = segoff.seg;
+ u8 *ptr_far = (u8*)(segoff.offset+0);
+ u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
+ SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
clear_usertimer();
} else {
// Continue waiting.
- time -= 0x3D1;
+ time -= USEC_PER_RTC;
SET_BDA(user_wait_timeout, time);
}
projects / seabios.git / blobdiff