// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2002 MandrakeSoft S.A.
//
-// This file may be distributed under the terms of the GNU GPLv3 license.
+// This file may be distributed under the terms of the GNU LGPLv3 license.
-#include "biosvar.h" // struct bregs
+#include "biosvar.h" // SET_BDA
#include "util.h" // debug_enter
#include "disk.h" // floppy_tick
#include "cmos.h" // inb_cmos
+#include "pic.h" // eoi_pic1
+#include "bregs.h" // struct bregs
+#include "biosvar.h" // GET_GLOBAL
+
+// RTC register flags
+#define RTC_A_UIP 0x80
+#define RTC_B_SET 0x80
+#define RTC_B_PIE 0x40
+#define RTC_B_AIE 0x20
+#define RTC_B_UIE 0x10
+
+// Bits for PORT_PS2_CTRLB
+#define PPCB_T2GATE (1<<0)
+#define PPCB_SPKR (1<<1)
+#define PPCB_T2OUT (1<<5)
+
+// Bits for PORT_PIT_MODE
+#define PM_SEL_TIMER0 (0<<6)
+#define PM_SEL_TIMER1 (1<<6)
+#define PM_SEL_TIMER2 (2<<6)
+#define PM_SEL_READBACK (3<<6)
+#define PM_ACCESS_LATCH (0<<4)
+#define PM_ACCESS_LOBYTE (1<<4)
+#define PM_ACCESS_HIBYTE (2<<4)
+#define PM_ACCESS_WORD (3<<4)
+#define PM_MODE0 (0<<1)
+#define PM_MODE1 (1<<1)
+#define PM_MODE2 (2<<1)
+#define PM_MODE3 (3<<1)
+#define PM_MODE4 (4<<1)
+#define PM_MODE5 (5<<1)
+#define PM_CNT_BINARY (0<<0)
+#define PM_CNT_BCD (1<<0)
+
+
+/****************************************************************
+ * TSC timer
+ ****************************************************************/
+
+#define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
+#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
+
+u32 cpu_khz VAR16_32;
-#define DEBUGF1(fmt, args...) bprintf(0, fmt , ##args)
-#define DEBUGF(fmt, args...)
+static void
+calibrate_tsc()
+{
+ // Setup "timer2"
+ u8 orig = inb(PORT_PS2_CTRLB);
+ outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
+ /* binary, mode 0, LSB/MSB, Ch 2 */
+ outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
+ /* LSB of ticks */
+ outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
+ /* MSB of ticks */
+ outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
+
+ u64 start = rdtscll();
+ while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
+ ;
+ u64 end = rdtscll();
+
+ // Restore PORT_PS2_CTRLB
+ outb(orig, PORT_PS2_CTRLB);
+
+ // Store calibrated cpu khz.
+ u64 diff = end - start;
+ dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
+ , (u32)start, (u32)end, (u32)diff);
+ u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
+ SET_GLOBAL(cpu_khz, hz / 1000);
+
+ dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
+}
+
+static void
+tscsleep(u64 diff)
+{
+ u64 start = rdtscll();
+ u64 end = start + diff;
+ while (rdtscll() < end)
+ cpu_relax();
+}
+
+void
+ndelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz / 1000000);
+}
+void
+udelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz / 1000);
+}
+void
+mdelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz);
+}
+
+// Return the TSC value that is 'msecs' time in the future.
+u64
+calc_future_tsc(u32 msecs)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ return rdtscll() + ((u64)khz * msecs);
+}
+
+
+/****************************************************************
+ * Init
+ ****************************************************************/
+
+static int
+rtc_updating()
+{
+ // This function checks to see if the update-in-progress bit
+ // is set in CMOS Status Register A. If not, it returns 0.
+ // If it is set, it tries to wait until there is a transition
+ // to 0, and will return 0 if such a transition occurs. A -1
+ // is returned only after timing out. The maximum period
+ // that this bit should be set is constrained to 244useconds, so
+ // we wait for 1 msec max.
+
+ if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ return 0;
+ u64 end = calc_future_tsc(1);
+ do {
+ if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ return 0;
+ } while (rdtscll() <= end);
+
+ // update-in-progress never transitioned to 0
+ return -1;
+}
static void
pit_setup()
{
// timer0: binary count, 16bit count, mode 2
- outb(0x34, PORT_PIT_MODE);
+ outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
// maximum count of 0000H = 18.2Hz
outb(0x0, PORT_PIT_COUNTER0);
outb(0x0, PORT_PIT_COUNTER0);
void
timer_setup()
{
+ dprintf(3, "init timer\n");
+ calibrate_tsc();
pit_setup();
+ rtc_updating();
u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
u32 ticks = (seconds * 18206507) / 1000000;
u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
ticks += (hours * 65543427) / 1000;
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0);
+
+ enable_hwirq(0, entry_08);
+ enable_hwirq(8, entry_70);
}
static void
inb_cmos(CMOS_STATUS_D);
}
-static u8
-rtc_updating()
-{
- // This function checks to see if the update-in-progress bit
- // is set in CMOS Status Register A. If not, it returns 0.
- // If it is set, it tries to wait until there is a transition
- // to 0, and will return 0 if such a transition occurs. A 1
- // is returned only after timing out. The maximum period
- // that this bit should be set is constrained to 244useconds.
- // The count I use below guarantees coverage or more than
- // this time, with any reasonable IPS setting.
- u16 count = 25000;
- while (--count != 0) {
- if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
- return 0;
- }
- return 1; // update-in-progress never transitioned to 0
-}
+/****************************************************************
+ * Standard clock functions
+ ****************************************************************/
// get current clock count
static void
u32 ticks = (regs->cx << 16) | regs->dx;
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0); // reset flag
+ // XXX - should use set_code_success()?
regs->ah = 0;
set_success(regs);
}
outb_cmos(regs->dh, CMOS_RTC_MONTH);
outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
outb_cmos(regs->ch, CMOS_CENTURY);
- u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
+ // clear halt-clock bit
+ u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
outb_cmos(val8, CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // AL = val last written to Reg B
outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
- outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
// enable Status Reg B alarm bit, clear halt clock bit
- outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
+ outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
set_success(regs);
}
// My assumption: RegB = (RegB & 01010111b)
u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
// clear clock-halt bit, disable alarm bit
- outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
+ outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // val last written to Reg B
set_success(regs);
void VISIBLE16
handle_1a(struct bregs *regs)
{
- //debug_enter(regs);
+ debug_enter(regs, DEBUG_HDL_1a);
switch (regs->ah) {
case 0x00: handle_1a00(regs); break;
case 0x01: handle_1a01(regs); break;
void VISIBLE16
handle_1c()
{
- //debug_enter(regs);
+ debug_isr(DEBUG_ISR_1c);
}
// INT 08h System Timer ISR Entry Point
void VISIBLE16
handle_08()
{
- //debug_isr();
- irq_enable();
+ debug_isr(DEBUG_ISR_08);
floppy_tick();
SET_BDA(timer_counter, counter);
// chain to user timer tick INT #0x1c
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x1c, &br);
+ u32 eax=0, flags;
+ call16_simpint(0x1c, &eax, &flags);
- irq_disable();
+ eoi_pic1();
+}
+
+
+/****************************************************************
+ * Periodic timer
+ ****************************************************************/
+
+static int
+set_usertimer(u32 usecs, u16 seg, u16 offset)
+{
+ if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
+ return -1;
+
+ // Interval not already set.
+ SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
+ SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
+ SET_BDA(user_wait_timeout, usecs);
+
+ // Turn on the Periodic Interrupt timer
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
- eoi_master_pic();
+ return 0;
+}
+
+static void
+clear_usertimer()
+{
+ // Turn off status byte.
+ SET_BDA(rtc_wait_flag, 0);
+ // Clear the Periodic Interrupt.
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
+}
+
+#define RET_ECLOCKINUSE 0x83
+
+// Wait for CX:DX microseconds
+void
+handle_1586(struct bregs *regs)
+{
+ // Use the rtc to wait for the specified time.
+ u8 statusflag = 0;
+ u32 count = (regs->cx << 16) | regs->dx;
+ int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
+ if (ret) {
+ set_code_fail(regs, RET_ECLOCKINUSE);
+ return;
+ }
+ irq_enable();
+ while (!statusflag)
+ cpu_relax();
+ irq_disable();
+ set_success(regs);
}
// Set Interval requested.
static void
handle_158300(struct bregs *regs)
{
- if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING) {
+ int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
+ if (ret)
// Interval already set.
- DEBUGF("int15: Func 83h, failed, already waiting.\n" );
set_code_fail(regs, RET_EUNSUPPORTED);
- }
- // Interval not already set.
- SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
- u32 v = (regs->es << 16) | regs->bx;
- SET_BDA(ptr_user_wait_complete_flag, v);
- v = (regs->dx << 16) | regs->cx;
- SET_BDA(user_wait_timeout, v);
-
- // Unmask IRQ8 so INT70 will get through.
- u8 irqDisable = inb(PORT_PIC2_DATA);
- outb(irqDisable & ~PIC2_IRQ8, PORT_PIC2_DATA);
- // Turn on the Periodic Interrupt timer
- u8 bRegister = inb_cmos(CMOS_STATUS_B);
- outb_cmos(CMOS_STATUS_B, bRegister | CSB_EN_ALARM_IRQ);
-
- set_success(regs); // XXX - no set ah?
+ else
+ set_success(regs);
}
// Clear interval requested
static void
handle_158301(struct bregs *regs)
{
- SET_BDA(rtc_wait_flag, 0); // Clear status byte
- // Turn off the Periodic Interrupt timer
- u8 bRegister = inb_cmos(CMOS_STATUS_B);
- outb_cmos(CMOS_STATUS_B, bRegister & ~CSB_EN_ALARM_IRQ);
- set_success(regs); // XXX - no set ah?
+ clear_usertimer();
+ set_success(regs);
}
static void
void VISIBLE16
handle_70()
{
- debug_isr();
+ debug_isr(DEBUG_ISR_70);
// Check which modes are enabled and have occurred.
u8 registerB = inb_cmos(CMOS_STATUS_B);
u8 registerC = inb_cmos(CMOS_STATUS_C);
- if (!(registerB & 0x60))
+ if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
goto done;
if (registerC & 0x20) {
// Handle Alarm Interrupt.
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x4a, &br);
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x4a, &eax, &flags);
}
if (!(registerC & 0x40))
goto done;
// Wait Interval (Int 15, AH=83) active.
u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
if (time < 0x3D1) {
- // Done waiting.
+ // Done waiting - write to specified flag byte.
u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
u16 segment = segoff >> 16;
u16 offset = segoff & 0xffff;
- // Turn off status byte.
- SET_BDA(rtc_wait_flag, 0);
- // Clear the Periodic Interrupt.
- outb_cmos(registerB & 0x37, CMOS_STATUS_B);
- // Write to specified flag byte.
u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
+
+ clear_usertimer();
} else {
// Continue waiting.
time -= 0x3D1;
}
done:
- eoi_both_pics();
+ eoi_pic2();
}
projects / seabios.git / blobdiff