// Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
// Copyright (C) 2002 MandrakeSoft S.A.
//
-// This file may be distributed under the terms of the GNU GPLv3 license.
+// This file may be distributed under the terms of the GNU LGPLv3 license.
#include "biosvar.h" // SET_BDA
#include "util.h" // debug_enter
#include "disk.h" // floppy_tick
#include "cmos.h" // inb_cmos
-#include "pic.h" // unmask_pic1
+#include "pic.h" // eoi_pic1
#include "bregs.h" // struct bregs
+#include "biosvar.h" // GET_GLOBAL
// RTC register flags
#define RTC_A_UIP 0x80
#define RTC_B_AIE 0x20
#define RTC_B_UIE 0x10
+// Bits for PORT_PS2_CTRLB
+#define PPCB_T2GATE (1<<0)
+#define PPCB_SPKR (1<<1)
+#define PPCB_T2OUT (1<<5)
+
+// Bits for PORT_PIT_MODE
+#define PM_SEL_TIMER0 (0<<6)
+#define PM_SEL_TIMER1 (1<<6)
+#define PM_SEL_TIMER2 (2<<6)
+#define PM_SEL_READBACK (3<<6)
+#define PM_ACCESS_LATCH (0<<4)
+#define PM_ACCESS_LOBYTE (1<<4)
+#define PM_ACCESS_HIBYTE (2<<4)
+#define PM_ACCESS_WORD (3<<4)
+#define PM_MODE0 (0<<1)
+#define PM_MODE1 (1<<1)
+#define PM_MODE2 (2<<1)
+#define PM_MODE3 (3<<1)
+#define PM_MODE4 (4<<1)
+#define PM_MODE5 (5<<1)
+#define PM_CNT_BINARY (0<<0)
+#define PM_CNT_BCD (1<<0)
+
+
+/****************************************************************
+ * TSC timer
+ ****************************************************************/
+
+#define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
+#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
+
+u32 cpu_khz VAR16_32;
+
+static void
+calibrate_tsc()
+{
+ // Setup "timer2"
+ u8 orig = inb(PORT_PS2_CTRLB);
+ outb((orig & ~PPCB_SPKR) | PPCB_T2GATE, PORT_PS2_CTRLB);
+ /* binary, mode 0, LSB/MSB, Ch 2 */
+ outb(PM_SEL_TIMER2|PM_ACCESS_WORD|PM_MODE0|PM_CNT_BINARY, PORT_PIT_MODE);
+ /* LSB of ticks */
+ outb(CALIBRATE_COUNT & 0xFF, PORT_PIT_COUNTER2);
+ /* MSB of ticks */
+ outb(CALIBRATE_COUNT >> 8, PORT_PIT_COUNTER2);
+
+ u64 start = rdtscll();
+ while ((inb(PORT_PS2_CTRLB) & PPCB_T2OUT) == 0)
+ ;
+ u64 end = rdtscll();
+
+ // Restore PORT_PS2_CTRLB
+ outb(orig, PORT_PS2_CTRLB);
+
+ // Store calibrated cpu khz.
+ u64 diff = end - start;
+ dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
+ , (u32)start, (u32)end, (u32)diff);
+ u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
+ SET_GLOBAL(cpu_khz, hz / 1000);
+
+ dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
+}
+
+static void
+tscsleep(u64 diff)
+{
+ u64 start = rdtscll();
+ u64 end = start + diff;
+ while (rdtscll() < end)
+ cpu_relax();
+}
+
+void
+ndelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz / 1000000);
+}
+void
+udelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz / 1000);
+}
+void
+mdelay(u32 count)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ tscsleep(count * khz);
+}
+
+// Return the TSC value that is 'msecs' time in the future.
+u64
+calc_future_tsc(u32 msecs)
+{
+ u32 khz = GET_GLOBAL(cpu_khz);
+ return rdtscll() + ((u64)khz * msecs);
+}
+
/****************************************************************
* Init
****************************************************************/
+static int
+rtc_updating()
+{
+ // This function checks to see if the update-in-progress bit
+ // is set in CMOS Status Register A. If not, it returns 0.
+ // If it is set, it tries to wait until there is a transition
+ // to 0, and will return 0 if such a transition occurs. A -1
+ // is returned only after timing out. The maximum period
+ // that this bit should be set is constrained to 244useconds, so
+ // we wait for 1 msec max.
+
+ if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ return 0;
+ u64 end = calc_future_tsc(1);
+ do {
+ if ((inb_cmos(CMOS_STATUS_A) & 0x80) == 0)
+ return 0;
+ } while (rdtscll() <= end);
+
+ // update-in-progress never transitioned to 0
+ return -1;
+}
+
static void
pit_setup()
{
// timer0: binary count, 16bit count, mode 2
- outb(0x34, PORT_PIT_MODE);
+ outb(PM_SEL_TIMER0|PM_ACCESS_WORD|PM_MODE2|PM_CNT_BINARY, PORT_PIT_MODE);
// maximum count of 0000H = 18.2Hz
outb(0x0, PORT_PIT_COUNTER0);
outb(0x0, PORT_PIT_COUNTER0);
timer_setup()
{
dprintf(3, "init timer\n");
+ calibrate_tsc();
pit_setup();
+ rtc_updating();
u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
u32 ticks = (seconds * 18206507) / 1000000;
u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0);
- // Enable IRQ0 (handle_08)
- unmask_pic1(PIC1_IRQ0);
+ enable_hwirq(0, entry_08);
+ enable_hwirq(8, entry_70);
}
static void
* Standard clock functions
****************************************************************/
-static u8
-rtc_updating()
-{
- // This function checks to see if the update-in-progress bit
- // is set in CMOS Status Register A. If not, it returns 0.
- // If it is set, it tries to wait until there is a transition
- // to 0, and will return 0 if such a transition occurs. A 1
- // is returned only after timing out. The maximum period
- // that this bit should be set is constrained to 244useconds.
- // The count I use below guarantees coverage or more than
- // this time, with any reasonable IPS setting.
-
- u16 count = 25000;
- while (--count != 0) {
- if ( (inb_cmos(CMOS_STATUS_A) & 0x80) == 0 )
- return 0;
- }
- return 1; // update-in-progress never transitioned to 0
-}
-
// get current clock count
static void
handle_1a00(struct bregs *regs)
u32 ticks = (regs->cx << 16) | regs->dx;
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0); // reset flag
+ // XXX - should use set_code_success()?
regs->ah = 0;
set_success(regs);
}
outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
- unmask_pic2(PIC2_IRQ8); // enable IRQ 8
// enable Status Reg B alarm bit, clear halt clock bit
outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
set_success(regs);
handle_08()
{
debug_isr(DEBUG_ISR_08);
- irq_enable();
floppy_tick();
SET_BDA(timer_counter, counter);
// chain to user timer tick INT #0x1c
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x1c, &br);
-
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x1c, &eax, &flags);
eoi_pic1();
}
SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
SET_BDA(user_wait_timeout, usecs);
- // Unmask IRQ8 so INT70 will get through.
- unmask_pic2(PIC2_IRQ8);
// Turn on the Periodic Interrupt timer
u8 bRegister = inb_cmos(CMOS_STATUS_B);
outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
}
-// Sleep for n microseconds.
-int
-usleep(u32 count)
+#define RET_ECLOCKINUSE 0x83
+
+// Wait for CX:DX microseconds
+void
+handle_1586(struct bregs *regs)
{
-#ifdef MODE16
- // In 16bit mode, use the rtc to wait for the specified time.
+ // Use the rtc to wait for the specified time.
u8 statusflag = 0;
+ u32 count = (regs->cx << 16) | regs->dx;
int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
- if (ret)
- return -1;
+ if (ret) {
+ set_code_fail(regs, RET_ECLOCKINUSE);
+ return;
+ }
irq_enable();
while (!statusflag)
cpu_relax();
irq_disable();
- return 0;
-#else
- // In 32bit mode, we need to call into 16bit mode to sleep.
- struct bregs br;
- memset(&br, 0, sizeof(br));
- br.ah = 0x86;
- br.cx = count >> 16;
- br.dx = count;
- call16_int(0x15, &br);
- if (br.flags & F_CF)
- return -1;
- return 0;
-#endif
-}
-
-#define RET_ECLOCKINUSE 0x83
-
-// Wait for CX:DX microseconds. currently using the
-// refresh request port 0x61 bit4, toggling every 15usec
-void
-handle_1586(struct bregs *regs)
-{
- int ret = usleep((regs->cx << 16) | regs->dx);
- if (ret)
- set_code_fail(regs, RET_ECLOCKINUSE);
- else
- set_success(regs);
+ set_success(regs);
}
// Set Interval requested.
goto done;
if (registerC & 0x20) {
// Handle Alarm Interrupt.
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x4a, &br);
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x4a, &eax, &flags);
}
if (!(registerC & 0x40))
goto done;
projects / seabios.git / blobdiff