#include "cmos.h" // inb_cmos
#include "pic.h" // eoi_pic1
#include "bregs.h" // struct bregs
+#include "biosvar.h" // GET_GLOBAL
// RTC register flags
#define RTC_A_UIP 0x80
#define PIT_TICK_RATE 1193182 // Underlying HZ of PIT
#define CALIBRATE_COUNT 0x800 // Approx 1.7ms
-extern u32 cpu_khz;
-#if MODE16
-u32 cpu_khz VISIBLE16;
-#endif
+u32 cpu_khz VAR16_32;
static void
calibrate_tsc()
dprintf(6, "tsc calibrate start=%u end=%u diff=%u\n"
, (u32)start, (u32)end, (u32)diff);
u32 hz = diff * PIT_TICK_RATE / CALIBRATE_COUNT;
- SET_VAR(CS, cpu_khz, hz / 1000);
+ SET_GLOBAL(cpu_khz, hz / 1000);
dprintf(1, "CPU Mhz=%u\n", hz / 1000000);
}
void
ndelay(u32 count)
{
- u32 khz = GET_VAR(CS, cpu_khz);
+ u32 khz = GET_GLOBAL(cpu_khz);
tscsleep(count * khz / 1000000);
}
void
udelay(u32 count)
{
- u32 khz = GET_VAR(CS, cpu_khz);
+ u32 khz = GET_GLOBAL(cpu_khz);
tscsleep(count * khz / 1000);
}
void
mdelay(u32 count)
{
- u32 khz = GET_VAR(CS, cpu_khz);
+ u32 khz = GET_GLOBAL(cpu_khz);
tscsleep(count * khz);
}
u64
calc_future_tsc(u32 msecs)
{
- u32 khz = GET_VAR(CS, cpu_khz);
+ u32 khz = GET_GLOBAL(cpu_khz);
return rdtscll() + ((u64)khz * msecs);
}
u32 ticks = (regs->cx << 16) | regs->dx;
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0); // reset flag
+ // XXX - should use set_code_success()?
regs->ah = 0;
set_success(regs);
}
handle_08()
{
debug_isr(DEBUG_ISR_08);
- irq_enable();
floppy_tick();
SET_BDA(timer_counter, counter);
// chain to user timer tick INT #0x1c
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x1c, &br);
-
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x1c, &eax, &flags);
eoi_pic1();
}
goto done;
if (registerC & 0x20) {
// Handle Alarm Interrupt.
- struct bregs br;
- memset(&br, 0, sizeof(br));
- call16_int(0x4a, &br);
- irq_disable();
+ u32 eax=0, flags;
+ call16_simpint(0x4a, &eax, &flags);
}
if (!(registerC & 0x40))
goto done;