//
// This file may be distributed under the terms of the GNU GPLv3 license.
-#include "biosvar.h" // struct bregs
+#include "biosvar.h" // SET_BDA
#include "util.h" // debug_enter
#include "disk.h" // floppy_tick
#include "cmos.h" // inb_cmos
+#include "pic.h" // unmask_pic1
+#include "bregs.h" // struct bregs
+
+// RTC register flags
+#define RTC_A_UIP 0x80
+#define RTC_B_SET 0x80
+#define RTC_B_PIE 0x40
+#define RTC_B_AIE 0x20
+#define RTC_B_UIE 0x10
+
+
+/****************************************************************
+ * Init
+ ****************************************************************/
+
+static void
+pit_setup()
+{
+ // timer0: binary count, 16bit count, mode 2
+ outb(0x34, PORT_PIT_MODE);
+ // maximum count of 0000H = 18.2Hz
+ outb(0x0, PORT_PIT_COUNTER0);
+ outb(0x0, PORT_PIT_COUNTER0);
+}
+
+static u32
+bcd2bin(u8 val)
+{
+ return (val & 0xf) + ((val >> 4) * 10);
+}
+
+void
+timer_setup()
+{
+ dprintf(3, "init timer\n");
+ pit_setup();
+
+ u32 seconds = bcd2bin(inb_cmos(CMOS_RTC_SECONDS));
+ u32 ticks = (seconds * 18206507) / 1000000;
+ u32 minutes = bcd2bin(inb_cmos(CMOS_RTC_MINUTES));
+ ticks += (minutes * 10923904) / 10000;
+ u32 hours = bcd2bin(inb_cmos(CMOS_RTC_HOURS));
+ ticks += (hours * 65543427) / 1000;
+ SET_BDA(timer_counter, ticks);
+ SET_BDA(timer_rollover, 0);
+
+ // Enable IRQ0 (handle_08)
+ unmask_pic1(PIC1_IRQ0);
+}
static void
init_rtc()
inb_cmos(CMOS_STATUS_D);
}
+
+/****************************************************************
+ * Standard clock functions
+ ****************************************************************/
+
static u8
rtc_updating()
{
regs->dx = ticks;
regs->al = GET_BDA(timer_rollover);
SET_BDA(timer_rollover, 0); // reset flag
- set_cf(regs, 0);
+ set_success(regs);
}
// Set Current Clock Count
SET_BDA(timer_counter, ticks);
SET_BDA(timer_rollover, 0); // reset flag
regs->ah = 0;
- set_cf(regs, 0);
+ set_success(regs);
}
// Read CMOS Time
handle_1a02(struct bregs *regs)
{
if (rtc_updating()) {
- set_cf(regs, 1);
+ set_fail(regs);
return;
}
regs->dl = inb_cmos(CMOS_STATUS_B) & 0x01;
regs->ah = 0;
regs->al = regs->ch;
- set_cf(regs, 0);
+ set_success(regs);
}
// Set CMOS Time
outb_cmos(val8, CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // val last written to Reg B
- set_cf(regs, 0);
+ set_success(regs);
}
// Read CMOS Date
{
regs->ah = 0;
if (rtc_updating()) {
- set_cf(regs, 1);
+ set_fail(regs);
return;
}
regs->cl = inb_cmos(CMOS_RTC_YEAR);
regs->dl = inb_cmos(CMOS_RTC_DAY_MONTH);
regs->ch = inb_cmos(CMOS_CENTURY);
regs->al = regs->ch;
- set_cf(regs, 0);
+ set_success(regs);
}
// Set CMOS Date
// My assumption: RegB = (RegB & 01111111b)
if (rtc_updating()) {
init_rtc();
- set_cf(regs, 1);
+ set_fail(regs);
return;
}
outb_cmos(regs->cl, CMOS_RTC_YEAR);
outb_cmos(regs->dh, CMOS_RTC_MONTH);
outb_cmos(regs->dl, CMOS_RTC_DAY_MONTH);
outb_cmos(regs->ch, CMOS_CENTURY);
- u8 val8 = inb_cmos(CMOS_STATUS_B) & 0x7f; // clear halt-clock bit
+ // clear halt-clock bit
+ u8 val8 = inb_cmos(CMOS_STATUS_B) & ~RTC_B_SET;
outb_cmos(val8, CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // AL = val last written to Reg B
- set_cf(regs, 0);
+ set_success(regs);
}
// Set Alarm Time in CMOS
regs->ax = 0;
if (val8 & 0x20) {
// Alarm interrupt enabled already
- set_cf(regs, 1);
+ set_fail(regs);
return;
}
if (rtc_updating()) {
outb_cmos(regs->dh, CMOS_RTC_SECONDS_ALARM);
outb_cmos(regs->cl, CMOS_RTC_MINUTES_ALARM);
outb_cmos(regs->ch, CMOS_RTC_HOURS_ALARM);
- outb(inb(PORT_PIC2_DATA) & ~PIC2_IRQ8, PORT_PIC2_DATA); // enable IRQ 8
+ unmask_pic2(PIC2_IRQ8); // enable IRQ 8
// enable Status Reg B alarm bit, clear halt clock bit
- outb_cmos((val8 & 0x7f) | 0x20, CMOS_STATUS_B);
- set_cf(regs, 0);
+ outb_cmos((val8 & ~RTC_B_SET) | RTC_B_AIE, CMOS_STATUS_B);
+ set_success(regs);
}
// Turn off Alarm
// My assumption: RegB = (RegB & 01010111b)
u8 val8 = inb_cmos(CMOS_STATUS_B); // Get Status Reg B
// clear clock-halt bit, disable alarm bit
- outb_cmos(val8 & 0x57, CMOS_STATUS_B); // disable alarm bit
+ outb_cmos(val8 & ~(RTC_B_SET|RTC_B_AIE), CMOS_STATUS_B);
regs->ah = 0;
regs->al = val8; // val last written to Reg B
- set_cf(regs, 0);
-}
-
-static void
-handle_1ab1(struct bregs *regs)
-{
- // XXX - pcibios stuff
- set_cf(regs, 1);
+ set_success(regs);
}
// Unsupported
static void
handle_1aXX(struct bregs *regs)
{
- set_cf(regs, 1);
+ set_fail(regs);
}
// INT 1Ah Time-of-day Service Entry Point
-void VISIBLE
+void VISIBLE16
handle_1a(struct bregs *regs)
{
- //debug_enter(regs);
+ debug_enter(regs, DEBUG_HDL_1a);
switch (regs->ah) {
case 0x00: handle_1a00(regs); break;
case 0x01: handle_1a01(regs); break;
case 0xb1: handle_1ab1(regs); break;
default: handle_1aXX(regs); break;
}
- debug_exit(regs);
}
// User Timer Tick
-void VISIBLE
-handle_1c(struct bregs *regs)
+void VISIBLE16
+handle_1c()
{
- debug_enter(regs);
+ debug_isr(DEBUG_ISR_1c);
}
// INT 08h System Timer ISR Entry Point
-void VISIBLE
-handle_08(struct bregs *regs)
+void VISIBLE16
+handle_08()
{
-// debug_enter(regs);
+ debug_isr(DEBUG_ISR_08);
+ irq_enable();
floppy_tick();
}
SET_BDA(timer_counter, counter);
- // XXX - int #0x1c
- eoi_master_pic();
+
+ // chain to user timer tick INT #0x1c
+ struct bregs br;
+ memset(&br, 0, sizeof(br));
+ call16_int(0x1c, &br);
+
+ irq_disable();
+
+ eoi_pic1();
+}
+
+
+/****************************************************************
+ * Periodic timer
+ ****************************************************************/
+
+static int
+set_usertimer(u32 usecs, u16 seg, u16 offset)
+{
+ if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
+ return -1;
+
+ // Interval not already set.
+ SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
+ SET_BDA(ptr_user_wait_complete_flag, (seg << 16) | offset);
+ SET_BDA(user_wait_timeout, usecs);
+
+ // Unmask IRQ8 so INT70 will get through.
+ unmask_pic2(PIC2_IRQ8);
+ // Turn on the Periodic Interrupt timer
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister | RTC_B_PIE, CMOS_STATUS_B);
+
+ return 0;
+}
+
+static void
+clear_usertimer()
+{
+ // Turn off status byte.
+ SET_BDA(rtc_wait_flag, 0);
+ // Clear the Periodic Interrupt.
+ u8 bRegister = inb_cmos(CMOS_STATUS_B);
+ outb_cmos(bRegister & ~RTC_B_PIE, CMOS_STATUS_B);
+}
+
+// Sleep for n microseconds.
+int
+usleep(u32 count)
+{
+ if (MODE16) {
+ // In 16bit mode, use the rtc to wait for the specified time.
+ u8 statusflag = 0;
+ int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
+ if (ret)
+ return -1;
+ irq_enable();
+ while (!statusflag)
+ cpu_relax();
+ irq_disable();
+ return 0;
+ } else {
+ // In 32bit mode, we need to call into 16bit mode to sleep.
+ struct bregs br;
+ memset(&br, 0, sizeof(br));
+ br.ah = 0x86;
+ br.cx = count >> 16;
+ br.dx = count;
+ call16_int(0x15, &br);
+ if (br.flags & F_CF)
+ return -1;
+ return 0;
+ }
+}
+
+#define RET_ECLOCKINUSE 0x83
+
+// Wait for CX:DX microseconds. currently using the
+// refresh request port 0x61 bit4, toggling every 15usec
+void
+handle_1586(struct bregs *regs)
+{
+ int ret = usleep((regs->cx << 16) | regs->dx);
+ if (ret)
+ set_code_fail(regs, RET_ECLOCKINUSE);
+ else
+ set_success(regs);
+}
+
+// Set Interval requested.
+static void
+handle_158300(struct bregs *regs)
+{
+ int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
+ if (ret)
+ // Interval already set.
+ set_code_fail(regs, RET_EUNSUPPORTED);
+ else
+ set_success(regs);
+}
+
+// Clear interval requested
+static void
+handle_158301(struct bregs *regs)
+{
+ clear_usertimer();
+ set_success(regs);
+}
+
+static void
+handle_1583XX(struct bregs *regs)
+{
+ set_code_fail(regs, RET_EUNSUPPORTED);
+ regs->al--;
+}
+
+void
+handle_1583(struct bregs *regs)
+{
+ switch (regs->al) {
+ case 0x00: handle_158300(regs); break;
+ case 0x01: handle_158301(regs); break;
+ default: handle_1583XX(regs); break;
+ }
}
// int70h: IRQ8 - CMOS RTC
-void VISIBLE
-handle_70(struct bregs *regs)
+void VISIBLE16
+handle_70()
{
- debug_enter(regs);
+ debug_isr(DEBUG_ISR_70);
+
+ // Check which modes are enabled and have occurred.
+ u8 registerB = inb_cmos(CMOS_STATUS_B);
+ u8 registerC = inb_cmos(CMOS_STATUS_C);
+
+ if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
+ goto done;
+ if (registerC & 0x20) {
+ // Handle Alarm Interrupt.
+ struct bregs br;
+ memset(&br, 0, sizeof(br));
+ call16_int(0x4a, &br);
+ irq_disable();
+ }
+ if (!(registerC & 0x40))
+ goto done;
+
+ // Handle Periodic Interrupt.
+
+ if (!GET_BDA(rtc_wait_flag))
+ goto done;
+
+ // Wait Interval (Int 15, AH=83) active.
+ u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
+ if (time < 0x3D1) {
+ // Done waiting - write to specified flag byte.
+ u32 segoff = GET_BDA(ptr_user_wait_complete_flag);
+ u16 segment = segoff >> 16;
+ u16 offset = segoff & 0xffff;
+ u8 oldval = GET_FARVAR(segment, *(u8*)(offset+0));
+ SET_FARVAR(segment, *(u8*)(offset+0), oldval | 0x80);
+
+ clear_usertimer();
+ } else {
+ // Continue waiting.
+ time -= 0x3D1;
+ SET_BDA(user_wait_timeout, time);
+ }
+
+done:
+ eoi_pic2();
}
projects / seabios.git / blobdiff