pc-com: nur dumpen bei enter und ein state removed

[hwmod.git] / src / calc_s3e.vhd

diff --git a/src/calc_s3e.vhd b/src/calc_s3e.vhd
index 040034ad3ec94bd49496f72f503241d0cd7d12b4..148be809c52981067999b1d44fbaa0f6eac63838 100644 (file)
--- a/src/calc_s3e.vhd
+++ b/src/calc_s3e.vhd
@@ -12,8 +12,8 @@ entity calc is
        port (
                CLK_50MHZ : in std_logic;
                sys_res : in std_logic;
-               -- btnA
-               -- TODO: pins
+               -- btnA (here: "btn west")
+               btn_a : in std_logic;
                -- rs232
                rxd : in std_logic;
                txd : out std_logic;
@@ -30,6 +30,8 @@ entity calc is
 end entity calc;
 
 architecture top of calc is
+       constant CLK_FREQ : integer := 50000000;
+       constant BAUDRATE : integer := 115200;
        -- reset
        signal sys_res_n : std_logic;
        -- ps/2
@@ -57,6 +59,12 @@ architecture top of calc is
        signal p_wdone : std_logic;
        signal p_write : hbyte;
        signal p_finished : std_logic;
+       --history/pc_com
+       signal pc_get : std_logic;
+       signal pc_spalte : hspalte;
+       signal pc_zeile : hzeile;
+       signal pc_char : hbyte;
+       signal pc_done : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
        -- rs232
@@ -68,7 +76,7 @@ begin
        sys_res_n <= not sys_res;
 
        -- vga/ipcore
-       textmode_vga_inst : entity work.textmode_vga(struct)
+       textmode_vga_inst : textmode_vga
        generic map (
                VGA_CLK_FREQ => 25000000,
                BLINK_INTERVAL_MS => 500,
@@ -90,14 +98,14 @@ begin
        );
 
        -- pll fuer vga
-       clk_vga_s3e_inst : entity work.clk_vga_s3e(beh)
+       clk_vga_s3e_inst : clk_vga_s3e
        port map (
                clk50 => CLK_50MHZ,
                clk25 => vga_clk
        );
 
        -- display
-       display_inst : entity work.display(beh)
+       display_inst : display
        port map (
                sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
@@ -117,7 +125,7 @@ begin
        );
 
        -- history
-       history_inst : entity work.history(beh)
+       history_inst : history
        port map (
                sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
@@ -142,11 +150,17 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- pc communication
+               pc_get =>  pc_get,
+               pc_spalte => pc_spalte,
+               pc_zeile => pc_zeile,
+               pc_char => pc_char,
+               pc_done => pc_done
        );
 
        -- parser
-       parser_inst : entity work.parser(beh)
+       parser_inst : parser
        port map (
                sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
@@ -164,7 +178,7 @@ begin
        );
 
        -- scanner
-       scanner_inst : entity work.scanner(beh)
+       scanner_inst : scanner
        port map (
                sys_clk => CLK_50MHZ,
                sys_res_n => sys_res_n,
@@ -182,9 +196,9 @@ begin
        );
 
        -- ps/2
-       ps2_inst : entity work.ps2_keyboard_controller(beh)
+       ps2_inst : ps2_keyboard_controller
        generic map (
-               CLK_FREQ => 50000000,
+               CLK_FREQ => CLK_FREQ,
                SYNC_STAGES => 2
        )
        port map (
@@ -198,7 +212,7 @@ begin
        );
 
        -- synchronizer fuer rxd
-       sync_rxd_inst : entity work.sync(beh)
+       sync_rxd_inst : sync
        generic map (
                SYNC_STAGES => 2,
                RESET_VALUE => '1'
@@ -211,10 +225,10 @@ begin
        );
 
        -- rs232-rx
-       rs232rx_inst : entity work.uart_rx(beh)
+       rs232rx_inst : uart_rx
        generic map (
-               CLK_FREQ => 50000000,
-               BAUDRATE => 115200
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
        )
        port map (
                sys_clk => CLK_50MHZ,
@@ -225,10 +239,10 @@ begin
        );
 
        -- rs232-tx
-       rs232tx_inst : entity work.uart_tx(beh)
+       rs232tx_inst : uart_tx
        generic map (
-               CLK_FREQ => 50000000,
-               BAUDRATE => 115200
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
        )
        port map (
                sys_clk => CLK_50MHZ,
@@ -238,4 +252,26 @@ begin
                tx_new => tx_new,
                tx_done => tx_done
        );
+
+       -- pc-com
+       pc_com_inst : pc_communication
+       port map (
+               sys_clk => CLK_50MHZ,
+               sys_res_n => sys_res_n,
+               --button
+               btn_a => not btn_a,
+               --uart_tx
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done,
+               --uart_rx
+               rx_data => rx_data,
+               rx_new => rx_new,
+               -- History
+               pc_zeile => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get => pc_get,
+               pc_done => pc_done,
+               pc_char => pc_char
+       );
 end architecture top;