use work.textmode_vga_pkg.all;
use work.textmode_vga_platform_dependent_pkg.all;
use work.ps2_keyboard_controller_pkg.all;
+use work.sync_pkg.all;
entity calc is
port (
-- btnA
-- TODO: pins
-- rs232
- -- TODO: pins
+ rxd : in std_logic;
+ txd : out std_logic;
-- vga
vsync_n : out std_logic;
hsync_n : out std_logic;
b : out std_logic_vector(BLUE_BITS - 1 downto 0);
-- ps/2
ps2_clk : inout std_logic;
- ps2_data : inout std_logic;
- -- debug
- led0 : out std_logic;
- led1 : out std_logic
+ ps2_data : inout std_logic
);
end entity calc;
-- history/scanner
signal s_char : hbyte;
signal s_take, s_done, s_backspace : std_logic;
-
- -- tmp: history<>scanner
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
signal do_it, finished : std_logic;
+ -- rs232
+ signal rx_new, rxd_sync : std_logic;
+ signal rx_data : std_logic_vector (7 downto 0);
+ signal tx_new, tx_done : std_logic;
+ signal tx_data : std_logic_vector (7 downto 0);
begin
- led0 <= '0';
- led1 <= '1';
sys_res_n <= not sys_res;
-- vga/ipcore
d_get => d_get,
d_done => d_done,
d_char => d_char,
- -- TODO: tmp only!
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished
+ );
+
+ -- parser
+ parser_inst : entity work.parser(beh)
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
do_it => do_it,
finished => finished
);
s_take => s_take,
s_done => s_done,
s_backspace => s_backspace,
- -- TODO: parser. temporaer mit history verbunden
+ -- parser
do_it => do_it,
finished => finished
);
ps2_clk => ps2_clk,
ps2_data => ps2_data
);
+
+ -- synchronizer fuer rxd
+ sync_rxd_inst : entity work.sync(beh)
+ generic map (
+ SYNC_STAGES => 2,
+ RESET_VALUE => '1'
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ data_in => rxd,
+ data_out => rxd_sync
+ );
+
+ -- rs232-rx
+ rs232rx_inst : entity work.uart_rx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ rxd => rxd_sync,
+ rx_data => rx_data,
+ rx_new => rx_new
+ );
+
+ -- rs232-tx
+ rs232tx_inst : entity work.uart_tx(beh)
+ generic map (
+ CLK_FREQ => 50000000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => CLK_50MHZ,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
end architecture top;