architecture sim of beh_uart_tx_tb is
- constant clk_period : time := 10ns;
+ constant clk_period : time := 2ns;
signal clock : std_logic;
signal reset : std_logic;
signal done : std_logic;
signal newsig : std_logic;
+ signal data : std_logic_vector(7 downto 0);
+ signal serial_out : std_logic;
begin
inst : entity work.uart_tx(beh)
port map (
- sys_clk => clock,
- sys_res => reset,
- --=> txd,
- --=> tx_data,
- tx_new => newsig,
- tx_done => done
+ sys_clk => clock,
+ sys_res => reset,
+ txd => serial_out,
+ tx_data => data,
+ tx_new => newsig,
+ tx_done => done
);
stimuli : process
newsig <= '0';
wait for 10ns;
--send 'Hallo Welt'
+ data <= X"42";
newsig <= '1';
wait for 1000ns;