Since some people disapprove of white space cleanups mixed in regular commits

[coreboot.git] / src / arch / i386 / coreboot_ram.ld

diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld
index 2b603ea7969d4d3b085239930af807fb5ce25657..2e602205ddfcc0f2b4d179144a73b877fc5a558d 100644 (file)
--- a/src/arch/i386/coreboot_ram.ld
+++ b/src/arch/i386/coreboot_ram.ld
@@ -1,11 +1,12 @@
 /*
  *     Memory map:
  *
- *     CONFIG_RAMBASE          
+ *     CONFIG_RAMBASE          : text segment
+ *                             : rodata segment
  *                             : data segment
  *                             : bss segment
- *                             : heap
  *                             : stack
+ *                             : heap
  */
 /*
  * Bootstrap code for the STPC Consumer
@@ -17,10 +18,8 @@
  *      Rewritten by Eric Biederman
  *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
  */
-/*
- *     We use ELF as output format. So that we can
- *     debug the code in some form. 
- */
+
+/* We use ELF as output format. So that we can debug the code in some form. */
 INCLUDE ldoptions
 
 ENTRY(_start)
@@ -28,9 +27,8 @@ ENTRY(_start)
 SECTIONS
 {
        . = CONFIG_RAMBASE;
-       /*
-        * First we place the code and read only data (typically const declared).
-        * This get placed in rom.
+       /* First we place the code and read only data (typically const declared).
+        * This could theoretically be placed in rom.
         */
        .text : {
                _text = .;
@@ -39,6 +37,7 @@ SECTIONS
                . = ALIGN(16);
                _etext = .;
        }
+
        .rodata : {
                _rodata = .;
                . = ALIGN(4);
@@ -54,17 +53,14 @@ SECTIONS
                ecpu_drivers = . ;
                *(.rodata)
                *(.rodata.*)
-               /*
-                * kevinh/Ispiri - Added an align, because the objcopy tool
+               /* kevinh/Ispiri - Added an align, because the objcopy tool
                 * incorrectly converts sections that are not long word aligned.
-                * This breaks the coreboot.rom target.
                 */
                 . = ALIGN(4);
 
                _erodata = .;
-       }       
-       /*
-        * After the code we place initialized data (typically initialized
+       }
+       /* After the code we place initialized data (typically initialized
         * global variables). This gets copied into ram by startup code.
         * __data_start and __data_end shows where in ram this should be placed,
         * whereas __data_loadstart and __data_loadend shows where in rom to
@@ -76,18 +72,7 @@ SECTIONS
                _edata = .;
        }
 
-       .sdata : {
-               _SDA_BASE_ = .;
-               *(.sdata)
-       }
-
-       .sdata2 : {
-               _SDA2_BASE_ = .;
-               *(.sdata2)
-       }
-
-       /*
-        * bss does not contain data, it is just a space that should be zero
+       /* bss does not contain data, it is just a space that should be zero
         * initialized on startup. (typically uninitialized global variables)
         * crt0.S fills between _bss and _ebss with zeroes.
         */
@@ -99,14 +84,20 @@ SECTIONS
        }
        _ebss = .;
        _end = .;
+
+       /* coreboot really "ends" here. Only heap and stack are placed after
+        * this line.
+        */
+
        . = ALIGN(CONFIG_STACK_SIZE);
+
        _stack = .;
        .stack . : {
                /* Reserve a stack for each possible cpu */
-               /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
-               . += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
+               . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE;
        }
        _estack = .;
+
         _heap = .;
         .heap . : {
                 /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
@@ -114,15 +105,34 @@ SECTIONS
                 . = ALIGN(4);
         }
         _eheap = .;
-       /* The ram segment
-        * This is all address of the memory resident copy of coreboot.
+
+       /* Some assertions to print human readable errors for certain linker
+        * error scenarios.
         */
-       _ram_seg = _text; 
+
+       /* Avoid running into 0xa0000-0xfffff */
+       _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
+
+       /* The ram segment. This includes all memory used by the memory
+        * resident copy of coreboot, except the tables that are produced on
+        * the fly, but including stack and heap.
+        */
+       _ram_seg = _text;
        _eram_seg = _eheap;
 
-       _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP");
+       /* CONFIG_RAMTOP is the upper address of cached memory (among other
+        * things). We must not exceed beyond that address, there be dragons.
+        */
+       _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
+
+       /* This rule is only good for the few broken targets that still live
+        * below 1MB per default. Those are the Geode and VIA targets that come
+        * with their own version of real mode switches that can't live above
+        * 1MB. Once these are fixed, this rule should go away.
+        */
+        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN || CONFIG_HAVE_SMI_HANDLER) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))), "Please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE to 1M");
 
-        _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M");
+       /* Discard the sections we don't need/want */
 
        /DISCARD/ : {
                *(.comment)