-
-/* 2006.1 yhlu add mptable cross 0x467 processing */
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003 Eric Biederman
+ * Copyright (C) 2005 Steve Magnani
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <console/console.h>
#include <cpu/cpu.h>
#include <boot/tables.h>
#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
#include <arch/pirq_routing.h>
#include <arch/smp/mpspec.h>
#include <arch/acpi.h>
#include <string.h>
-#include "coreboot_table.h"
-
-// Global Descriptor Table, defined in c_start.S
-extern uint8_t gdt;
-extern uint8_t gdt_end;
-
-/* i386 lgdt argument */
-struct gdtarg {
- unsigned short limit;
- unsigned int base;
-} __attribute__((packed));
-
-// Copy GDT to new location and reload it
-// 2003-07 by SONE Takeshi
-// Ported from Etherboot to coreboot 2005-08 by Steve Magnani
-void move_gdt(unsigned long newgdt)
+#include <cpu/x86/multiboot.h>
+#include <cbmem.h>
+#include <lib.h>
+
+uint64_t high_tables_base = 0;
+uint64_t high_tables_size;
+
+void cbmem_arch_init(void)
{
- uint16_t num_gdt_bytes = &gdt_end - &gdt;
- struct gdtarg gdtarg;
-
- printk_debug("Moving GDT to %#lx...", newgdt);
- memcpy((void*)newgdt, &gdt, num_gdt_bytes);
- gdtarg.base = newgdt;
- gdtarg.limit = num_gdt_bytes - 1;
- __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg));
- printk_debug("ok\n");
+ /* defined in gdt.c */
+ move_gdt();
}
struct lb_memory *write_tables(void)
{
- unsigned long low_table_start, low_table_end, new_low_table_end;
+ unsigned long low_table_start, low_table_end;
unsigned long rom_table_start, rom_table_end;
- rom_table_start = 0xf0000;
+ /* Even if high tables are configured, some tables are copied both to
+ * the low and the high area, so payloads and OSes don't need to know
+ * about the high tables.
+ */
+ unsigned long high_table_pointer;
+
+ if (!high_tables_base) {
+ printk(BIOS_ERR, "ERROR: High Tables Base is not set.\n");
+ // Are there any boards without?
+ // Stepan thinks we should die() here!
+ }
+
+ printk(BIOS_DEBUG, "High Tables Base is %llx.\n", high_tables_base);
+
+ rom_table_start = 0xf0000;
rom_table_end = 0xf0000;
- /* Start low addr at 16 bytes instead of 0 because of a buglet
- * in the generic linux unzip code, as it tests for the a20 line.
+
+ /* Start low addr at 0x500, so we don't run into conflicts with the BDA
+ * in case our data structures grow beyound 0x400. Only multiboot, GDT
+ * and the coreboot table use low_tables.
*/
low_table_start = 0;
- low_table_end = 16;
+ low_table_end = 0x500;
+#if CONFIG_GENERATE_PIRQ_TABLE == 1
+#define MAX_PIRQ_TABLE_SIZE (4 * 1024)
post_code(0x9a);
- /* This table must be betweeen 0xf0000 & 0x100000 */
+ /* This table must be between 0x0f0000 and 0x100000 */
rom_table_end = write_pirq_routing_table(rom_table_end);
- rom_table_end = (rom_table_end + 1023) & ~1023;
+ rom_table_end = ALIGN(rom_table_end, 1024);
- /* Write ACPI tables */
- /* write them in the rom area because DSDT can be large (8K on epia-m) which
- * pushes coreboot table out of first 4K if set up in low table area
+ /* And add a high table version for those payloads that
+ * want to live in the F segment
*/
- rom_table_end = write_acpi_tables(rom_table_end);
- rom_table_end = (rom_table_end+1023) & ~1023;
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_PIRQ, MAX_PIRQ_TABLE_SIZE);
+ if (high_table_pointer) {
+ unsigned long new_high_table_pointer;
+ new_high_table_pointer = write_pirq_routing_table(high_table_pointer);
+ // FIXME make pirq table code intelligent enough to know how
+ // much space it's going to need.
+ if (new_high_table_pointer > (high_table_pointer + MAX_PIRQ_TABLE_SIZE)) {
+ printk(BIOS_ERR, "ERROR: Increase PIRQ size.\n");
+ }
+ printk(BIOS_DEBUG, "PIRQ table: %ld bytes.\n",
+ new_high_table_pointer - high_table_pointer);
+ }
+
+#endif
- /* copy the smp block to address 0 */
- post_code(0x96);
+#if CONFIG_GENERATE_MP_TABLE == 1
+#define MAX_MP_TABLE_SIZE (4 * 1024)
+ post_code(0x9b);
/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
- new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
-
-#if HAVE_MP_TABLE==1
- /* Don't write anything in the traditional x86 BIOS data segment,
- * for example the linux kernel smp need to use 0x467 to pass reset vector
- * or use 0x40e/0x413 for EBDA finding...
- */
- if(new_low_table_end>0x400){
- unsigned mptable_size;
- unsigned mpc_start;
- low_table_end += SMP_FLOATING_TABLE_LEN; /* keep the mpf in 1k low, so kernel can find it */
- mptable_size = new_low_table_end - low_table_end;
- /* We can not put mptable low, we need to copy them to somewhere else*/
- if((rom_table_end+mptable_size)<0x100000) {
- /* We can copy mptable on rom_table */
- mpc_start = rom_table_end;
- rom_table_end += mptable_size;
- rom_table_end = (rom_table_end+1023) & ~1023;
+ rom_table_end = write_smp_table(rom_table_end);
+ rom_table_end = ALIGN(rom_table_end, 1024);
+
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE, MAX_MP_TABLE_SIZE);
+ if (high_table_pointer) {
+ unsigned long new_high_table_pointer;
+ new_high_table_pointer = write_smp_table(high_table_pointer);
+ // FIXME make mp table code intelligent enough to know how
+ // much space it's going to need.
+ if (new_high_table_pointer > (high_table_pointer + MAX_MP_TABLE_SIZE)) {
+ printk(BIOS_ERR, "ERROR: Increase MP table size.\n");
+ }
+
+ printk(BIOS_DEBUG, "MP table: %ld bytes.\n",
+ new_high_table_pointer - high_table_pointer);
+ }
+#endif /* CONFIG_GENERATE_MP_TABLE */
+
+#if CONFIG_GENERATE_ACPI_TABLES == 1
+#define MAX_ACPI_SIZE (47 * 1024)
+ post_code(0x9c);
+
+ /* Write ACPI tables to F segment and high tables area */
+
+ /* Ok, this is a bit hacky still, because some day we want to have this
+ * completely dynamic. But right now we are setting fixed sizes.
+ * It's probably still better than the old high_table_base code because
+ * now at least we know when we have an overflow in the area.
+ *
+ * We want to use 1MB - 64K for Resume backup. We use 512B for TOC and
+ * 512 byte for GDT, 4K for PIRQ and 4K for MP table and 8KB for the
+ * coreboot table. This leaves us with 47KB for all of ACPI. Let's see
+ * how far we get.
+ */
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_ACPI, MAX_ACPI_SIZE);
+ if (high_table_pointer) {
+ unsigned long acpi_start = high_table_pointer;
+ unsigned long new_high_table_pointer;
+
+ rom_table_end = ALIGN(rom_table_end, 16);
+ new_high_table_pointer = write_acpi_tables(high_table_pointer);
+ if (new_high_table_pointer > ( high_table_pointer + MAX_ACPI_SIZE)) {
+ printk(BIOS_ERR, "ERROR: Increase ACPI size\n");
+ }
+ printk(BIOS_DEBUG, "ACPI tables: %ld bytes.\n",
+ new_high_table_pointer - high_table_pointer);
+
+ /* Now we need to create a low table copy of the RSDP. */
+
+ /* First we look for the high table RSDP */
+ while (acpi_start < new_high_table_pointer) {
+ if (memcmp(((acpi_rsdp_t *)acpi_start)->signature, RSDP_SIG, 8) == 0) {
+ break;
+ }
+ acpi_start++;
+ }
+
+ /* Now, if we found the RSDP, we take the RSDT and XSDT pointer
+ * from it in order to write the low RSDP
+ */
+ if (acpi_start < new_high_table_pointer) {
+ acpi_rsdp_t *low_rsdp = (acpi_rsdp_t *)rom_table_end,
+ *high_rsdp = (acpi_rsdp_t *)acpi_start;
+
+ acpi_write_rsdp(low_rsdp,
+ (acpi_rsdt_t *)(high_rsdp->rsdt_address),
+ (acpi_xsdt_t *)((unsigned long)high_rsdp->xsdt_address));
} else {
- /* We can need to put mptable before rom_table */
- mpc_start = rom_table_start - mptable_size;
- mpc_start &= ~1023;
- rom_table_start = mpc_start;
+ printk(BIOS_ERR, "ERROR: Didn't find RSDP in high table.\n");
}
- printk_debug("move mptable from 0x%0x to 0x%0x, size 0x%0x\n", low_table_end, mpc_start, mptable_size);
- memcpy((unsigned char *)mpc_start, (unsigned char *)low_table_end, mptable_size);
- smp_write_floating_table_physaddr(low_table_end - SMP_FLOATING_TABLE_LEN, mpc_start);
- memset((unsigned char *)low_table_end, '\0', mptable_size);
+ rom_table_end = ALIGN(rom_table_end + sizeof(acpi_rsdp_t), 16);
+ } else {
+ rom_table_end = write_acpi_tables(rom_table_end);
+ rom_table_end = ALIGN(rom_table_end, 1024);
}
+
#endif
- if (low_table_end < 0x500) {
- low_table_end = 0x500;
- }
+#if CONFIG_MULTIBOOT
+ post_code(0x9d);
+
+ /* The Multiboot information structure */
+ rom_table_end = write_multiboot_info(
+ low_table_start, low_table_end,
+ rom_table_start, rom_table_end);
+#endif
+
+#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+ post_code(0x9d);
- // Relocate the GDT to reserved memory, so it won't get clobbered
- move_gdt(low_table_end);
- low_table_end += &gdt_end - &gdt;
+ high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
- /* The coreboot table must be in 0-4K or 960K-1M */
- write_coreboot_table(low_table_start, low_table_end,
+ if (high_table_pointer) {
+ unsigned long new_high_table_pointer;
+
+ /* Also put a forwarder entry into 0-4K */
+ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end,
+ high_tables_base, high_table_pointer);
+
+ if (new_high_table_pointer > (high_table_pointer +
+ MAX_COREBOOT_TABLE_SIZE))
+ printk(BIOS_ERR, "%s: coreboot table didn't fit (%lx)\n",
+ __func__, new_high_table_pointer -
+ high_table_pointer);
+
+ printk(BIOS_DEBUG, "coreboot table: %ld bytes.\n",
+ new_high_table_pointer - high_table_pointer);
+ } else {
+ /* The coreboot table must be in 0-4K or 960K-1M */
+ write_coreboot_table(low_table_start, low_table_end,
rom_table_start, rom_table_end);
+ }
+
+ post_code(0x9e);
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* Let's prepare the ACPI S3 Resume area now already, so we can rely on
+ * it begin there during reboot time. We don't need the pointer, nor
+ * the result right now. If it fails, ACPI resume will be disabled.
+ */
+ cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64));
+#endif
+
+ // Remove before sending upstream
+ cbmem_list();
return get_lb_mem();
}
projects / coreboot.git / blobdiff