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Unify crt0s setup to src/arch/i386/Makefile.inc. This variable
[coreboot.git] / src / arch / i386 / Makefile.inc
diff --git a/src/arch/i386/Makefile.inc b/src/arch/i386/Makefile.inc
index ef4b90af0c28615809326845ef68ea64d12f25d9..2b17671ee11ed9d849ecf1fa1bc50f12b777a708 100644 (file)
--- a/src/arch/i386/Makefile.inc
+++ b/src/arch/i386/Makefile.inc
@@ -1,7 +1,7 @@
 #######################################################################
 # Take care of subdirectories
 subdirs-y += boot
-subdirs-y += init
+# subdirs-y += init
 subdirs-y += lib
 subdirs-y += smp
 
@@ -15,14 +15,14 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL)
        cp $(obj)/coreboot.pre $@
        if [ -f fallback/coreboot_apc ]; \
        then \
-               $(CBFSTOOL) $@ add-stage fallback/coreboot_apc fallback/coreboot_apc $(CBFS_COMPRESS_FLAG); \
+               $(CBFSTOOL) $@ add-stage fallback/coreboot_apc $(CONFIG_CBFS_PREFIX)/coreboot_apc $(CBFS_COMPRESS_FLAG); \
        fi
-       $(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram fallback/coreboot_ram $(CBFS_COMPRESS_FLAG)
+       $(CBFSTOOL) $@ add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
        @printf "    PAYLOAD    none (as specified by user)\n"
 else
        @printf "    PAYLOAD    $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n"
-       $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
+       $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
 endif
 ifeq ($(CONFIG_VGA_BIOS),y)
        @printf "    VGABIOS    $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n"
@@ -45,9 +45,9 @@ $(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc8
 #######################################################################
 # Build the coreboot_ram (stage 2)
 
-$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
+$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/arch/i386/coreboot_ram.ld #ldoptions
        @printf "    CC         $(subst $(obj)/,,$(@))\n"
-       $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
+       $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/i386/coreboot_ram.ld $(obj)/coreboot_ram.o
        $(NM) -n $(obj)/coreboot_ram | sort > $(obj)/coreboot_ram.map
 
 $(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
@@ -62,10 +62,129 @@ $(obj)/coreboot.a: $(objs)
 #######################################################################
 # done
 
+crt0s :=
+ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
+crt0s += $(src)/cpu/x86/16bit/entry16.inc
+endif
+crt0s += $(src)/cpu/x86/32bit/entry32.inc
+ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
+crt0s += $(src)/cpu/x86/16bit/reset16.inc
+ifeq ($(CONFIG_ROMCC),y)
+crt0s += $(src)/arch/i386/lib/cpu_reset.inc
+endif
+crt0s += $(src)/arch/i386/lib/id.inc
+endif
+
+crt0s += $(src)/cpu/x86/fpu_enable.inc
+ifeq ($(CONFIG_CPU_AMD_GX1),y)
+crt0s += $(src)/cpu/amd/model_gx1/cpu_setup.inc
+crt0s += $(src)/cpu/amd/model_gx1/gx_setup.inc
+endif
+ifeq ($(CONFIG_SSE),y)
+crt0s += $(src)/cpu/x86/sse_enable.inc
+endif
+
+ifeq ($(CONFIG_CPU_AMD_LX),y)
+crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_F),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_F_1207),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_AM2),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_S1G1),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_754),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_939),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_AMD_SOCKET_940),y)
+crt0s += $(src)/cpu/amd/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_CPU_INTEL_CORE),y)
+crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+endif
+# Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
+ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y)
+crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+endif
+# should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet
+ifeq ($(CONFIG_BOARD_VIA_VT8454C),y)
+crt0s += $(src)/cpu/via/car/cache_as_ram.inc
+endif
+ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y)
+crt0s += $(src)/cpu/via/car/cache_as_ram.inc
+endif
+# who else could use this?
+ifeq ($(CONFIG_BOARD_TYAN_S2735),y)
+crt0s += $(src)/cpu/x86/car/cache_as_ram.inc
+endif
+
+ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
+ifeq ($(CONFIG_ROMCC),y)
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/failover.inc
+endif
+endif
+crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
+
+ifeq ($(CONFIG_SSE),y)
+crt0s += $(src)/cpu/x86/sse_disable.inc
+endif
+ifeq ($(CONFIG_MMX),y)
+crt0s += $(src)/cpu/x86/mmx_disable.inc
+endif
+
+ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
+ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_CK804),y)
+crt0s += $(src)/southbridge/nvidia/ck804/romstrap.inc
+endif
+ifeq ($(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55),y)
+crt0s += $(src)/southbridge/nvidia/mcp55/romstrap.inc
+endif
+ifeq ($(CONFIG_SOUTHBRIDGE_VIA_K8T890),y)
+crt0s += $(src)/southbridge/via/k8t890/romstrap.inc
+endif
+ifeq ($(CONFIG_NORTHBRIDGE_VIA_VX800),y)
+crt0s += $(src)/northbridge/via/vx800/romstrap.inc
+endif
+endif
+
+OPTION_TABLE_H:=
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+OPTION_TABLE_H:=$(obj)/option_table.h
+endif
+
+ifeq ($(CONFIG_ROMCC),y)
+ROMCCFLAGS ?= -mcpu=p2 -O2
+
+$(obj)/mainboard/$(MAINBOARDDIR)/failover.inc: $(obj)/romcc $(src)/arch/i386/lib/failover.c
+       $(obj)/romcc $(ROMCCFLAGS) --label-prefix=failover $(INCLUDES) $(src)/arch/i386/lib/failover.c -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h
+       $(obj)/romcc $(ROMCCFLAGS) -include $(obj)/build.h $(INCLUDES) $< -o $@
+
+else
+
+$(obj)/mainboard/$(MAINBOARDDIR)/ap_romstage.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(obj)/option_table.h
+       $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S  $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@
+
+$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h
+       $(CC) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -include $(obj)/build.h -I$(src) -I. -c -S $< -o $@.tmp1
+       sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $@.tmp1 > $@.tmp
+       mv $@.tmp $@
+       rm -f $@.tmp1
+endif
 endif
 
 ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
-include $(src)/arch/i386/Makefile.tinybootblock.inc
+include $(src)/arch/i386/Makefile.bootblock.inc
 else
 include $(src)/arch/i386/Makefile.bigbootblock.inc
 endif
my coreboot WIP stuff (asus m5a99x-evo board)