alu/sync: warum hat sich da keiner der beiden tools aufgeregt? wird das nicht sonst...

[hwmod.git] / src / alu_tb.vhd

diff --git a/src/alu_tb.vhd b/src/alu_tb.vhd
index df488b60ab9adb8fb5b3a698c1760455b4399e7c..1b0d2f4ab3f3947b543e45c666c62fc7db20d33c 100644 (file)
--- a/src/alu_tb.vhd
+++ b/src/alu_tb.vhd
@@ -4,7 +4,7 @@ use ieee.numeric_std.all;
 use work.gen_pkg.all;
 
 entity alu_tb is
-       end entity alu_tb;
+end entity alu_tb;
 
 architecture sim of alu_tb is
        component alu is
@@ -17,14 +17,13 @@ architecture sim of alu_tb is
                        op2 : in csigned;
                        op3 : out csigned;
                        do_calc : in std_logic;
-                       ack : in std_logic;
                        calc_done : out std_logic
                );
        end component alu;
 
-       signal sys_clk, sys_res_n, do_calc, calc_done, ack : std_logic;
+       signal sys_clk, sys_res_n, do_calc, calc_done : std_logic;
        signal opcode : alu_ops;
-       signal op1, op2, op3, optmp : csigned;
+       signal op1, op2, op3 : csigned;
        signal stop : boolean := false;
 begin
        bla : alu
@@ -33,7 +32,6 @@ begin
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
                do_calc => do_calc,
-               ack => ack,
                calc_done => calc_done,
                op1 => op1,
                op2 => op2,
@@ -46,37 +44,76 @@ begin
                sys_clk <= '0';
                wait for 15 ns;
                sys_clk <= '1';
+               wait for 15 ns;
                if stop = true then
                        wait;
                end if;
-               wait for 15 ns;
        end process;
 
        process
+               type alu_testv is record
+                       o1 : cinteger;
+                       o : alu_ops;
+                       o2 : cinteger;
+                       expected : cinteger;
+               end record alu_testv;
+
+               -- ggf. groesse des arrays erhoehen
+               type alu_testv_array is array (natural range 0 to 20) of alu_testv;
+
+               variable testmatrix : alu_testv_array :=
+                       ( 0 => (-5, DIV, 3, -1),
+                         1 => (7, ADD, 3, 10),
+                         2 => (7, SUB, 1, 6),
+                         3 => (7, DIV, 1, 7),
+                         4 => (7, DIV, 3, 2),
+                         5 => (7, ADD, 1, 8),
+                         6 => (7, MUL, 3, 21),
+                         7 => (-7, MUL, 3, -21),
+                         8 => (268435456, MUL, -2, -536870912),
+                         9 => (268435456, MUL, 2**5, 0), -- um fuenf nach links shiften
+                         10 => (268435456 + 5, MUL, 2**5, 160), -- = 5 * (2^5)
+                         11 => (100, DIV, 10, 10),
+                         12 => (100, DIV, 51, 1),
+                         13 => (100, DIV, 49, 2),
+                         14 => (153156, DIV, 3543, 43),
+                         15 => (-153156, DIV, 3543, -43),
+                         16 => (153156, DIV, -3543, -43),
+                         17 => (-153156, DIV, -3543, 43),
+                         others => (0, ADD, 0, 0)
+                       );
+
        begin
                sys_res_n <= '0';
                wait for 50 ns;
                sys_res_n <= '1';
-               wait for 100 ns;
 
-               op1(31 downto 0) <= (0 => '1', 1 => '1', 2 => '1', others => '0');
-               op2(31 downto 0) <= (0 => '1', 2 => '1', others => '0');
-               opcode <= ADD;
+               for i in testmatrix'range loop
+                       wait for 100 ns;
+                       op1 <= to_signed(testmatrix(i).o1,CBITS);
+                       opcode <= testmatrix(i).o;
+                       op2 <= to_signed(testmatrix(i).o2,CBITS);
 
-               wait for 10 ns;
-               -- berechnung kann los gehen
-               do_calc <= '1';
-               ack <= '0';
+                       -- berechnung kann los gehen
+                       do_calc <= '1';
 
-               -- warten auf die alu einheit
-               wait on calc_done;
+                       -- warten auf die alu einheit
+                       wait on calc_done;
 
-               -- ack it!
-               do_calc <= '0';
-               ack <= '1';
+                       assert op3 = to_signed(testmatrix(i).expected,CBITS)
+                               report "" & cinteger'image(testmatrix(i).o1) & 
+                               " " & alu_ops'image(opcode) &
+                               " " & cinteger'image(testmatrix(i).o2) &
+                               "/= " & integer'image(to_integer(op3)) &
+                               " -- erwartet: " & cinteger'image(testmatrix(i).expected);
 
-               wait for 20 ns;
+                       wait for 5 ns;
+                       -- ack it!
+                       do_calc <= '0';
+               end loop;
 
+               assert false
+                       report "alle testfaelle der ALU waren erfolgreich!";
                stop <= true;
                wait;
        end process;