# o source files der module
# o reihenfolge ist wichtig
# o keine testbechnes hier angeben
-SRCFILES := alu parser scanner
+SRCFILES := alu parser scanner display sp_ram history uart_tx uart_rx
# o files der packages
# o keine testbechnes hier angeben
-PKGFILES = gen_pkg math_pkg
+PKGFILES = math_pkg gen_pkg
PKGFILES += textmode_vga/textmode_vga_platform_dependent_pkg
PKGFILES += textmode_vga/textmode_vga_pkg
PKGFILES += textmode_vga/font_pkg
$(D_BEHSIM)/$(WORK)/%/_primary.dat: %.vhd $(D_BEHSIM)/modelsim.ini
@echo " CC $<"
- @cd $(D_BEHSIM); \
- vcom -work $(WORK) $(MPWD)/$<
+ cd $(D_BEHSIM); \
+ vcom -cover bcest -work $(WORK) $(MPWD)/$<
beh_%: $(D_BEHSIM)/$(WORK)/beh_%_tb/_primary.dat beh_%_tb.do behsim
cd $(D_BEHSIM); \
- vsim "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
+ vsim -coverage "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
#postsim
postsim: $(POST_VHO) $(POST_SDO)