help
Enable this option if you are working on the sconfig
device tree parser and made changes to sconfig.l and
- sconfig.y.
+ sconfig.y.
Otherwise, say N.
config USE_OPTION_TABLE
Enable this option if coreboot shall read options from the "CMOS"
NVRAM instead of using hard coded values.
+config COMPRESS_RAMSTAGE
+ bool "Compress ramstage with LZMA"
+ default y
+ help
+ Compress ramstage to save memory in the flash image. Note
+ that decompression might slow down booting if the boot flash
+ is connected through a slow Link (i.e. SPI)
+
+config INCLUDE_CONFIG_FILE
+ bool "Include the coreboot config file into the ROM image"
+ default y
+ help
+ Include in CBFS the coreboot config file that was used to compile the ROM image
+
+config EARLY_CBMEM_INIT
+ bool "Initialize CBMEM while in ROM stage"
+ default n
+ help
+ Make coreboot initialize the cbmem structures while running in rom
+ stage. This could be useful when the rom stage wants to communicate
+ some, for instance, execution timestamps.
+
+config COLLECT_TIMESTAMPS
+ bool "Create a table of timestamps collected during boot"
+ depends on EARLY_CBMEM_INIT
+ help
+ Make coreboot create a table of timer id/timer value pairs to
+ allow measuring time spent at different phases of the boot
+ process.
endmenu
source src/mainboard/Kconfig
int
default 0
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0x0
config PCI_ROM_RUN
bool
default n
bool
default n
-config ATI_RAGE_XL
+source src/console/Kconfig
+
+# This should default to N and be set by SuperI/O drivers that have an UART
+config HAVE_UART_IO_MAPPED
bool
+ default y
-source src/console/Kconfig
+config HAVE_UART_MEMORY_MAPPED
+ bool
+ default n
config HAVE_ACPI_RESUME
bool
bool
default n
+config TPM
+ bool
+ default n
+
# TODO: Can probably be removed once all chipsets have kconfig options for it.
config VIDEO_MB
int
bool
default HAVE_PIRQ_TABLE
+config GENERATE_SMBIOS_TABLES
+ bool
+ default y
+
menu "System tables"
config WRITE_HIGH_TABLES
If unsure, say Y.
+config GENERATE_SMBIOS_TABLES
+ depends on ARCH_X86
+ bool "Generate SMBIOS tables"
+ default y
+ help
+ Generate SMBIOS tables for this board.
+
+ If unsure, say Y.
+
endmenu
menu "Payload"
See http://coreboot.org/Payloads for more information.
+config PAYLOAD_FILO
+ bool "FILO"
+ help
+ Select this option if you want to build a coreboot image
+ with a FILO payload. If you don't know what this is
+ about, just leave it enabled.
+
+ See http://coreboot.org/Payloads for more information.
+
endchoice
choice
Newest SeaBIOS version
endchoice
+choice
+ prompt "FILO version"
+ default FILO_STABLE
+ depends on PAYLOAD_FILO
+
+config FILO_STABLE
+ bool "0.6.0"
+ help
+ Stable FILO version
+config FILO_MASTER
+ bool "HEAD"
+ help
+ Newest FILO version
+endchoice
+
config PAYLOAD_FILE
string "Payload path and filename"
depends on PAYLOAD_ELF
config PAYLOAD_FILE
depends on PAYLOAD_SEABIOS
- default "payloads/external/SeaBIOS/seabios/out/bios.bin.elf"
+ default "$(obj)/seabios/out/bios.bin.elf"
+
+config PAYLOAD_FILE
+ depends on PAYLOAD_FILO
+ default "payloads/external/FILO/filo/build/filo.elf"
# TODO: Defined if no payload? Breaks build?
config COMPRESSED_PAYLOAD_LZMA
bool "Use LZMA compression for payloads"
default y
- depends on PAYLOAD_ELF || PAYLOAD_SEABIOS
+ depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO
help
In order to reduce the size payloads take up in the ROM chip
coreboot can compress them using the LZMA algorithm.
endmenu
-menu "Bootsplash"
- depends on PCI_OPTION_ROM_RUN_YABEL
+menu "Display"
+ depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
-config BOOTSPLASH
- prompt "Show graphical bootsplash"
+config FRAMEBUFFER_SET_VESA_MODE
+ prompt "Set VESA framebuffer mode"
bool
- depends on PCI_OPTION_ROM_RUN_YABEL
- help
- This option shows a graphical bootsplash screen. The grapics are
- loaded from the CBFS file bootsplash.jpg.
-
-config BOOTSPLASH_FILE
- string "Bootsplash path and filename"
- depends on BOOTSPLASH
- default "bootsplash.jpg"
+ depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
help
- The path and filename of the file to use as graphical bootsplash
- screen. The file format has to be jpg.
+ Set VESA framebuffer mode (needed for bootsplash)
# TODO: Turn this into a "choice".
config FRAMEBUFFER_VESA_MODE
prompt "VESA framebuffer video mode"
hex
default 0x117
- depends on BOOTSPLASH
+ depends on FRAMEBUFFER_SET_VESA_MODE
help
- This option sets the resolution used for the coreboot framebuffer and
- bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
+ This option sets the resolution used for the coreboot framebuffer (and
+ bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
some day make this a "choice".
-config COREBOOT_KEEP_FRAMEBUFFER
+config FRAMEBUFFER_KEEP_VESA_MODE
prompt "Keep VESA framebuffer"
bool
- depends on BOOTSPLASH
+ depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
help
This option keeps the framebuffer mode set after coreboot finishes
execution. If this option is enabled, coreboot will pass a
framebuffer driver. If this option is disabled, coreboot will switch
back to text mode before handing control to a payload.
+config BOOTSPLASH
+ prompt "Show graphical bootsplash"
+ bool
+ depends on FRAMEBUFFER_SET_VESA_MODE
+ help
+ This option shows a graphical bootsplash screen. The grapics are
+ loaded from the CBFS file bootsplash.jpg.
+
+config BOOTSPLASH_FILE
+ string "Bootsplash path and filename"
+ depends on BOOTSPLASH
+ default "bootsplash.jpg"
+ help
+ The path and filename of the file to use as graphical bootsplash
+ screen. The file format has to be jpg.
endmenu
menu "Debugging"
# TODO: Better help text and detailed instructions.
config GDB_STUB
bool "GDB debugging support"
- default y
+ default n
help
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/x86/lib/c_start.S for details.
If unsure, say N.
endif
+config DEBUG_ACPI
+ def_bool n
+
+# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional
+# printk(BIOS_DEBUG, ...) calls.
+if DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8
+config DEBUG_ACPI
+ bool "Output verbose ACPI debug messages"
+ default n
+ help
+ This option enables additional ACPI related debug messages.
+
+ Note: This option will slightly increase the size of the coreboot image.
+
+ If unsure, say N.
+endif
+
config REALMODE_DEBUG
def_bool n
depends on PCI_OPTION_ROM_RUN_REALMODE
Put llshell() in your (romstage) code to start the shell.
See src/arch/x86/llshell/llshell.inc for details.
+config TRACE
+ bool "Trace function calls"
+ default n
+ help
+ If enabled, every function will print information to console once
+ the function is entered. The syntax is ~0xaaaabbbb(0xccccdddd)
+ the 0xaaaabbbb is the actual function and 0xccccdddd is EIP
+ of calling function. Please note some printk releated functions
+ are omitted from trace to have good looking console dumps.
endmenu
config LIFT_BSP_APIC_ID
bool
default y
-config ID_SECTION_OFFSET
- hex
- default 0x10
-
# The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE,
# POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are
# mutually exclusive. One of these options must be selected in the
Internal option that controls ENABLE_POWER_BUTTON visibility.
source src/Kconfig.deprecated_options
+source src/vendorcode/Kconfig