##
-## This file is part of the coreboot repair project.
+## This file is part of the coreboot project.
##
-## Redistribution and use in source and binary forms, with or without
-## modification, are permitted provided that the following conditions
-## are met:
-## 1. Redistributions of source code must retain the above copyright
-## notice, this list of conditions and the following disclaimer.
-## 2. Redistributions in binary form must reproduce the above copyright
-## notice, this list of conditions and the following disclaimer in the
-## documentation and/or other materials provided with the distribution.
-## 3. The name of the author may not be used to endorse or promote products
-## derived from this software without specific prior written permission.
+## Copyright (C) 2009-2010 coresystems GmbH
##
-## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
-## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
-## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
-## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-## SUCH DAMAGE.
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
mainmenu "Coreboot Configuration"
+menu "General setup"
+
+config EXPERT
+ bool "Expert mode"
+ help
+ This allows you to select certain advanced configuration options.
+
+ Warning: Only enable this option if you really know what you are
+ doing! You have been warned!
+
+config LOCALVERSION
+ string "Local version string"
+ help
+ Append an extra string to the end of the coreboot version.
+
+ This can be useful if, for instance, you want to append the
+ respective board's hostname or some other identifying string to
+ the coreboot version number, so that you can easily distinguish
+ boot logs of different boards from each other.
+
+config CBFS_PREFIX
+ string "CBFS prefix to use"
+ default "fallback"
+ help
+ Select the prefix to all files put into the image. It's "fallback"
+ by default, "normal" is a common alternative.
+
+config SCANBUILD_ENABLE
+ bool "build with scan-build for static analysis"
+ default n
+ help
+ Changes the build process to scan-build is used.
+ Requires scan-build in path.
+
+config SCANBUILD_REPORT_LOCATION
+ string "directory to put scan-build report in"
+ default ""
+ depends on SCANBUILD_ENABLE
+ help
+ Where the scan-build report should be stored
+
+endmenu
+
source src/mainboard/Kconfig
source src/arch/i386/Kconfig
-source src/arch/ppc/Kconfig
-source src/devices/Kconfig
+
+menu "Chipset"
+
+comment "CPU"
+source src/cpu/Kconfig
+comment "Northbridge"
+
+menu "HyperTransport setup"
+ depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
+
+choice
+ prompt "HyperTransport frequency"
+ default LIMIT_HT_SPEED_AUTO
+ help
+ This option sets the maximum permissible HyperTransport link
+ frequency.
+
+ Use of this option will only limit the autodetected HT frequency.
+ It will not (and cannot) increase the frequency beyond the
+ autodetected limits.
+
+ This is primarily used to work around poorly designed or laid out
+ HT traces on certain motherboards.
+
+config LIMIT_HT_SPEED_200
+ bool "Limit HT frequency to 200MHz"
+config LIMIT_HT_SPEED_400
+ bool "Limit HT frequency to 400MHz"
+config LIMIT_HT_SPEED_600
+ bool "Limit HT frequency to 600MHz"
+config LIMIT_HT_SPEED_800
+ bool "Limit HT frequency to 800MHz"
+config LIMIT_HT_SPEED_1000
+ bool "Limit HT frequency to 1.0GHz"
+config LIMIT_HT_SPEED_1200
+ bool "Limit HT frequency to 1.2GHz"
+config LIMIT_HT_SPEED_1400
+ bool "Limit HT frequency to 1.4GHz"
+config LIMIT_HT_SPEED_1600
+ bool "Limit HT frequency to 1.6GHz"
+config LIMIT_HT_SPEED_1800
+ bool "Limit HT frequency to 1.8GHz"
+config LIMIT_HT_SPEED_2000
+ bool "Limit HT frequency to 2.0GHz"
+config LIMIT_HT_SPEED_2200
+ bool "Limit HT frequency to 2.2GHz"
+config LIMIT_HT_SPEED_2400
+ bool "Limit HT frequency to 2.4GHz"
+config LIMIT_HT_SPEED_2600
+ bool "Limit HT frequency to 2.6GHz"
+config LIMIT_HT_SPEED_AUTO
+ bool "Autodetect HT frequency"
+endchoice
+
+choice
+ prompt "HyperTransport downlink width"
+ default LIMIT_HT_DOWN_WIDTH_16
+ help
+ This option sets the maximum permissible HyperTransport
+ downlink width.
+
+ Use of this option will only limit the autodetected HT width.
+ It will not (and cannot) increase the width beyond the autodetected
+ limits.
+
+ This is primarily used to work around poorly designed or laid out HT
+ traces on certain motherboards.
+
+config LIMIT_HT_DOWN_WIDTH_8
+ bool "8 bits"
+config LIMIT_HT_DOWN_WIDTH_16
+ bool "16 bits"
+endchoice
+
+choice
+ prompt "HyperTransport uplink width"
+ default LIMIT_HT_UP_WIDTH_16
+ help
+ This option sets the maximum permissible HyperTransport
+ uplink width.
+
+ Use of this option will only limit the autodetected HT width.
+ It will not (and cannot) increase the width beyond the autodetected
+ limits.
+
+ This is primarily used to work around poorly designed or laid out HT
+ traces on certain motherboards.
+
+config LIMIT_HT_UP_WIDTH_8
+ bool "8 bits"
+config LIMIT_HT_UP_WIDTH_16
+ bool "16 bits"
+endchoice
+
+endmenu
+
source src/northbridge/Kconfig
+comment "Southbridge"
source src/southbridge/Kconfig
+comment "Super I/O"
source src/superio/Kconfig
-source src/cpu/Kconfig
-
-config CBFS
- bool
- default y
+comment "Devices"
+source src/devices/Kconfig
-config HAVE_HIGH_TABLES
- bool
- default y
+endmenu
config PCI_BUS_SEGN_BITS
int
config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
hex
- default 0
+ default 0x0
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0
+ default 0x0
config CPU_ADDR_BITS
int
default 126
config LOGICAL_CPUS
- int
- default 1
+ bool
+ default y
config PCI_ROM_RUN
bool
default n
-config HT_CHAIN_UNITID_BASE
- int
- default 1
-
-config HT_CHAIN_END_UNITID_BASE
- int
- default 32
-
config HEAP_SIZE
hex
- default 0x2000
-
-config COREBOOT_V2
- bool
- default y
-
-config COREBOOT_V4
- bool
- default y
+ default 0x4000
config DEBUG
bool
bool
default n
-config LB_MEM_TOPK
- int
- default 2048
-
-config MULTIBOOT
- bool
- default n
-
-config COMPRESSED_PAYLOAD_LZMA
- bool
- default y
+config RAMTOP
+ hex
+ default 0x200000
-config COMPRESSED_PAYLOAD_NRV2B
+config ATI_RAGE_XL
bool
- default n
source src/console/Kconfig
int
default 0
-config HAVE_ACPI_TABLES
- bool
- default n
-
config HAVE_FALLBACK_BOOT
bool
default y
bool
default y
-config HAVE_HARD_RESET
+config HAVE_FAILOVER_BOOT
bool
default n
-config HAVE_INIT_TIMER
+config USE_FAILOVER_IMAGE
bool
default n
-config HAVE_MAINBOARD_RESOURCES
+config HAVE_HARD_RESET
bool
+ default y if BOARD_HAS_HARD_RESET
default n
+ help
+ This variable specifies whether a given board has a hard_reset
+ function, no matter if it's provided by board code or chipset code.
-config HAVE_MOVNTI
+config BOARD_HAS_HARD_RESET
bool
- default y
+ default n
+ help
+ This variable specifies whether a given board has a reset.c
+ file containing a hard_reset() function.
-config HAVE_MP_TABLE
+config BOARD_HAS_FADT
bool
default n
+ help
+ This variable specifies whether a given board has a board-local
+ FADT in fadt.c. Long-term, those should be moved to appropriate
+ chipset components (eg. southbridge)
-config HAVE_OPTION_TABLE
+config HAVE_BUS_CONFIG
bool
+ default n
+ help
+ This variable specifies whether a given board has a get_bus_conf.c
+ file containing bus configuration data.
+
+config HAVE_INIT_TIMER
+ bool
+ default n if UDELAY_IO
default y
-config HAVE_PIRQ_TABLE
+config HAVE_MAINBOARD_RESOURCES
bool
default n
+config HAVE_OPTION_TABLE
+ bool
+ default y
+ help
+ This variable specifies whether a given board has a cmos.layout
+ file containing NVRAM/CMOS bit definitions.
+ It defaults to 'y' but can be changed to 'n' in mainboard/*/Kconfig.
+
config PIRQ_ROUTE
bool
default n
bool
default n
+# TODO: Can probably be removed once all chipsets have kconfig options for it.
+config VIDEO_MB
+ int
+ default 0
+
+config USE_WATCHDOG_ON_BOOT
+ bool
+ default n
+
+config VGA
+ bool
+ default n
+ help
+ Build board-specific VGA code.
+
+config GFXUMA
+ bool
+ default n
+ help
+ Enable Unified Memory Architecture for graphics.
+
# TODO
# menu "Drivers"
-#
+#
# endmenu
-menu "Payload"
+#TODO Remove this option or make it useful.
+config HAVE_LOW_TABLES
+ bool
+ default y
+ help
+ This Option is unused in the code. Since two boards try to set it to
+ 'n', they may be broken. We either need to make the option useful or
+ get rid of it. The broken boards are:
+ asus/m2v-mx_se
+ supermicro/h8dme
-config COMPRESSED_PAYLOAD_LZMA
- bool "Use LZMA compression for payloads"
- default yes
+config HAVE_HIGH_TABLES
+ bool
+ default y
+ help
+ This variable specifies whether a given northbridge has high table
+ support.
+ It is set in northbridge/*/Kconfig.
+ Whether or not the high tables are actually written by coreboot is
+ configurable by the user via WRITE_HIGH_TABLES.
-choice
- prompt "Payload type"
- default PAYLOAD_NONE
+config HAVE_ACPI_TABLES
+ bool
+ help
+ This variable specifies whether a given board has ACPI table support.
+ It is usually set in mainboard/*/Kconfig.
+ Whether or not the ACPI tables are actually generated by coreboot
+ is configurable by the user via GENERATE_ACPI_TABLES.
-config PAYLOAD_ELF
- bool "An ELF executable payload file"
+config HAVE_MP_TABLE
+ bool
help
- Select this option if you have a payload image (an ELF file)
- which coreboot should run as soon as the basic hardware
- initialization is completed.
+ This variable specifies whether a given board has MP table support.
+ It is usually set in mainboard/*/Kconfig.
+ Whether or not the MP table is actually generated by coreboot
+ is configurable by the user via GENERATE_MP_TABLE.
- You will be able to specify the location and file name of the
- payload image later.
+config HAVE_PIRQ_TABLE
+ bool
+ help
+ This variable specifies whether a given board has PIRQ table support.
+ It is usually set in mainboard/*/Kconfig.
+ Whether or not the PIRQ table is actually generated by coreboot
+ is configurable by the user via GENERATE_PIRQ_TABLE.
-config VGA_BIOS
- bool "Add a VGA BIOS image"
- depends on PAYLOAD_ELF
+#These Options are here to avoid "undefined" warnings.
+#The actual selection and help texts are in the following menu.
+
+config GENERATE_ACPI_TABLES
+ bool
+ default HAVE_ACPI_TABLES
+
+config GENERATE_MP_TABLE
+ bool
+ default HAVE_MP_TABLE
+
+config GENERATE_PIRQ_TABLE
+ bool
+ default HAVE_PIRQ_TABLE
+
+config WRITE_HIGH_TABLES
+ bool
+ default HAVE_HIGH_TABLES
+
+menu "System tables"
+
+config WRITE_HIGH_TABLES
+ bool "Write 'high' tables to avoid being overwritten in F segment"
+ depends on HAVE_HIGH_TABLES
+ default y
+
+config MULTIBOOT
+ bool "Generate Multiboot tables (for GRUB2)"
+ default y
+
+config GENERATE_ACPI_TABLES
+ depends on HAVE_ACPI_TABLES
+ bool "Generate ACPI tables"
+ default y
help
- Select this option if you have a VGA BIOS image that you would
- like to add to your ROM.
+ Generate ACPI tables for this board.
- You will be able to specify the location and file name of the
- image later.
+ If unsure, say Y.
+
+config GENERATE_MP_TABLE
+ depends on HAVE_MP_TABLE
+ bool "Generate an MP table"
+ default y
+ help
+ Generate an MP table (conforming to the Intel MultiProcessor
+ specification 1.4) for this board.
+
+ If unsure, say Y.
+
+config GENERATE_PIRQ_TABLE
+ depends on HAVE_PIRQ_TABLE
+ bool "Generate a PIRQ table"
+ default y
+ help
+ Generate a PIRQ table for this board.
+
+ If unsure, say Y.
+
+endmenu
+
+menu "Payload"
+
+choice
+ prompt "Add a payload"
+ default PAYLOAD_NONE
config PAYLOAD_NONE
- bool "No payload"
+ bool "None"
help
Select this option if you want to create an "empty" coreboot
ROM image for a certain mainboard, i.e. a coreboot ROM image
which does not yet contain a payload.
- For such an image to be useful, you have to use the 'cbfs' tool
+ For such an image to be useful, you have to use 'cbfstool'
to add a payload to the ROM image later.
+config PAYLOAD_ELF
+ bool "An ELF executable payload"
+ help
+ Select this option if you have a payload image (an ELF file)
+ which coreboot should run as soon as the basic hardware
+ initialization is completed.
+
+ You will be able to specify the location and file name of the
+ payload image later.
+
endchoice
config FALLBACK_PAYLOAD_FILE
help
The path and filename of the ELF executable file to use as payload.
+# TODO: Defined if no payload? Breaks build?
+config COMPRESSED_PAYLOAD_LZMA
+ bool "Use LZMA compression for payloads"
+ default y
+ depends on PAYLOAD_ELF
+ help
+ In order to reduce the size payloads take up in the ROM chip
+ coreboot can compress them using the LZMA algorithm.
+
+config COMPRESSED_PAYLOAD_NRV2B
+ bool
+ default n
+
+endmenu
+
+menu "VGA BIOS"
+
+config VGA_BIOS
+ bool "Add a VGA BIOS image"
+ help
+ Select this option if you have a VGA BIOS image that you would
+ like to add to your ROM.
+
+ You will be able to specify the location and file name of the
+ image later.
+
config FALLBACK_VGA_BIOS_FILE
string "VGA BIOS path and filename"
depends on VGA_BIOS
The path and filename of the file to use as VGA BIOS.
config FALLBACK_VGA_BIOS_ID
- string "VGA BIOS ID"
+ string "VGA device PCI IDs"
depends on VGA_BIOS
default "1106,3230"
help
- The ID that would associate your VGA BIOS to your video card.
+ The comma-separated PCI vendor and device ID that would associate
+ your VGA BIOS to your video card.
+
+ Example: 1106,3230
+
+ In the above example 1106 is the PCI vendor ID (in hex, but without
+ the "0x" prefix) and 3230 specifies the PCI device ID of the
+ video card (also in hex, without "0x" prefix).
+
+config INTEL_MBI
+ bool "Add an MBI image"
+ depends on NORTHBRIDGE_INTEL_I82830
+ help
+ Select this option if you have an Intel MBI image that you would
+ like to add to your ROM.
+
+ You will be able to specify the location and file name of the
+ image later.
+
+config FALLBACK_MBI_FILE
+ string "Intel MBI path and filename"
+ depends on INTEL_MBI
+ default "mbi.bin"
+ help
+ The path and filename of the file to use as VGA BIOS.
+
+endmenu
+
+menu "Bootsplash"
+ depends on PCI_OPTION_ROM_RUN_YABEL
+
+config BOOTSPLASH
+ prompt "Show graphical bootsplash"
+ bool
+ depends on PCI_OPTION_ROM_RUN_YABEL
+ help
+ This option shows a graphical bootsplash screen. The grapics are
+ loaded from the CBFS file bootsplash.jpg.
+
+config FALLBACK_BOOTSPLASH_FILE
+ string "Bootsplash path and filename"
+ depends on BOOTSPLASH
+ default "bootsplash.jpg"
+ help
+ The path and filename of the file to use as graphical bootsplash
+ screen. The file format has to be jpg.
+
+# TODO: Turn this into a "choice".
+config FRAMEBUFFER_VESA_MODE
+ prompt "VESA framebuffer video mode"
+ hex
+ default 0x117
+ depends on BOOTSPLASH
+ help
+ This option sets the resolution used for the coreboot framebuffer and
+ bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
+ some day make this a "choice".
+
+config COREBOOT_KEEP_FRAMEBUFFER
+ prompt "Keep VESA framebuffer"
+ bool
+ depends on BOOTSPLASH
+ help
+ This option keeps the framebuffer mode set after coreboot finishes
+ execution. If this option is enabled, coreboot will pass a
+ framebuffer entry in its coreboot table and the payload will need a
+ framebuffer driver. If this option is disabled, coreboot will switch
+ back to text mode before handing control to a payload.
endmenu
+menu "Debugging"
+
+# TODO: Better help text and detailed instructions.
config GDB_STUB
bool "GDB debugging support"
default y
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/i386/lib/c_start.S for details.
+config DEBUG_RAM_SETUP
+ bool "Output verbose RAM init debug messages"
+ default n
+ depends on (NORTHBRIDGE_AMD_AMDFAM10 \
+ || NORTHBRIDGE_AMD_AMDK8 \
+ || NORTHBRIDGE_VIA_CN700 \
+ || NORTHBRIDGE_VIA_CX700 \
+ || NORTHBRIDGE_VIA_VX800 \
+ || NORTHBRIDGE_INTEL_E7501 \
+ || NORTHBRIDGE_INTEL_I440BX \
+ || NORTHBRIDGE_INTEL_I82810 \
+ || NORTHBRIDGE_INTEL_I82830 \
+ || NORTHBRIDGE_INTEL_I945)
+ help
+ This option enables additional RAM init related debug messages.
+ It is recommended to enable this when debugging issues on your
+ board which might be RAM init related.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config DEBUG_SMBUS
+ bool "Output verbose SMBus debug messages"
+ default n
+ depends on (SOUTHBRIDGE_VIA_VT8237R \
+ || NORTHBRIDGE_VIA_VX800 \
+ || NORTHBRIDGE_VIA_CX700 \
+ || NORTHBRIDGE_AMD_AMDK8)
+ help
+ This option enables additional SMBus (and SPD) debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config DEBUG_SMI
+ bool "Output verbose SMI debug messages"
+ default n
+ depends on HAVE_SMI_HANDLER
+ help
+ This option enables additional SMI related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG
+ bool "Output verbose x86emu debug messages"
+ default n
+ depends on PCI_OPTION_ROM_RUN_YABEL
+ help
+ This option enables additional x86emu related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_JMP
+ bool "Trace JMP/RETF"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print information about JMP and RETF opcodes from x86emu.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_TRACE
+ bool "Trace all opcodes"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print _all_ opcodes that are executed by x86emu.
+
+ WARNING: This will produce a LOT of output and take a long time.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_PNP
+ bool "Log Plug&Play accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print Plug And Play accesses made by option ROMs.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_DISK
+ bool "Log Disk I/O"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print Disk I/O related messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_PMM
+ bool "Log PMM"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to POST Memory Manager (PMM).
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+
+config X86EMU_DEBUG_VBE
+ bool "Debug VESA BIOS Extensions"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to VESA BIOS Extension (VBE) functions.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_INT10
+ bool "Redirect INT10 output to console"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Let INT10 (i.e. character output) calls print messages to debug output.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_INTERRUPTS
+ bool "Log intXX calls"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to interrupt handling.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_CHECK_VMEM_ACCESS
+ bool "Log special memory accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to accesses to certain areas of the virtual
+ memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_MEM
+ bool "Log all memory accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print memory accesses made by option ROM.
+ Note: This also includes accesses to fetch instructions.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_IO
+ bool "Log IO accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print I/O accesses made by option ROM.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config LLSHELL
+ bool "Built-in low-level shell"
+ default n
+ help
+ If enabled, you will have a low level shell to examine your machine.
+ Put llshell() in your (romstage) code to start the shell.
+ See src/arch/i386/llshell/llshell.inc for details.
+
+endmenu
+
+config LIFT_BSP_APIC_ID
+ bool
+ default n
+
+# These probably belong somewhere else, but they are needed somewhere.
+config AP_CODE_IN_CAR
+ bool
+ default n
+
+config USE_INIT
+ bool
+ default n
+
+config ENABLE_APIC_EXT_ID
+ bool
+ default n
+
+config WARNINGS_ARE_ERRORS
+ bool
+ default n
+
+config ID_SECTION_OFFSET
+ hex
+ default 0x10