Enables the use of ccache for faster builds.
Requires ccache in path.
+config USE_OPTION_TABLE
+ bool "Use CMOS for configuration values"
+ default n
+ help
+ Enable this option if coreboot shall read options from the "CMOS"
+ NVRAM instead of using hard coded values.
+
endmenu
source src/mainboard/Kconfig
endmenu
+menu "Generic Drivers"
+source src/drivers/Kconfig
+endmenu
+
config PCI_BUS_SEGN_BITS
int
default 0
hex
default 0x4000
-config DEBUG
- bool
- default n
-
config USE_PRINTK_IN_CAR
bool
default n
-config USE_OPTION_TABLE
- bool "Use CMOS for configuration values"
- default n
-
config MAX_CPUS
int
default 1
bool
default n
+config HAVE_ACPI_SLIC
+ bool
+ default n
+
config ACPI_SSDTX_NUM
int
default 0
If unsure, say N.
+config DEBUG_PIRQ
+ bool "Check PIRQ table consistency"
+ default n
+ depends on GENERATE_PIRQ_TABLE
+ help
+ If unsure, say N.
+
config DEBUG_SMBUS
bool "Output verbose SMBus debug messages"
default n
|| NORTHBRIDGE_VIA_CX700 \
|| NORTHBRIDGE_AMD_AMDK8 \
|| NORTHBRIDGE_AMD_AMDFAM10 \
+ || BOARD_LIPPERT_SPACERUNNER_LX \
|| SOUTHBRIDGE_VIA_VT8231)
help
This option enables additional SMBus (and SPD) debug messages.