Select the prefix to all files put into the image. It's "fallback"
by default, "normal" is a common alternative.
-endmenu
-
-source src/mainboard/Kconfig
-source src/arch/i386/Kconfig
-
-menu "Chipset"
-
-comment "CPU"
-source src/cpu/Kconfig
-comment "Northbridge"
-
-menu "HyperTransport Setup"
- depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT
-
-choice
- prompt "HyperTransport Frequency"
- default LIMIT_HT_SPEED_AUTO
- help
- This option sets the maximum permissible HyperTransport link frequency.
- Use of this option will only limit the autodetected HT frequency; it will not (and cannot) increase the frequency beyond the autodetected limits.
- This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
-
-config LIMIT_HT_SPEED_200
- bool "Limit HT frequency to 200MHz"
-config LIMIT_HT_SPEED_400
- bool "Limit HT frequency to 400MHz"
-config LIMIT_HT_SPEED_600
- bool "Limit HT frequency to 600MHz"
-config LIMIT_HT_SPEED_800
- bool "Limit HT frequency to 800MHz"
-config LIMIT_HT_SPEED_1000
- bool "Limit HT frequency to 1.0GHz"
-config LIMIT_HT_SPEED_1200
- bool "Limit HT frequency to 1.2GHz"
-config LIMIT_HT_SPEED_1400
- bool "Limit HT frequency to 1.4GHz"
-config LIMIT_HT_SPEED_1600
- bool "Limit HT frequency to 1.6GHz"
-config LIMIT_HT_SPEED_1800
- bool "Limit HT frequency to 1.6GHz"
-config LIMIT_HT_SPEED_2000
- bool "Limit HT frequency to 2.0GHz"
-config LIMIT_HT_SPEED_2200
- bool "Limit HT frequency to 2.2GHz"
-config LIMIT_HT_SPEED_2400
- bool "Limit HT frequency to 2.4GHz"
-config LIMIT_HT_SPEED_2600
- bool "Limit HT frequency to 2.6GHz"
-config LIMIT_HT_SPEED_AUTO
- bool "Autodetect HT frequency"
-endchoice
-
choice
- prompt "HyperTransport Downlink Width"
- default LIMIT_HT_DOWN_WIDTH_16
+ prompt "Compiler"
+ default COMPILER_GCC
help
- This option sets the maximum permissible HyperTransport link width.
- Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits.
- This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
+ This option allows you to select the compiler used for building
+ coreboot.
-config LIMIT_HT_DOWN_WIDTH_8
- bool "8 bits"
-config LIMIT_HT_DOWN_WIDTH_16
- bool "16 bits"
+config COMPILER_GCC
+ bool "GCC"
+config COMPILER_LLVM_CLANG
+ bool "LLVM/clang"
endchoice
-choice
- prompt "HyperTransport Uplink Width"
- default LIMIT_HT_UP_WIDTH_16
+config SCANBUILD_ENABLE
+ bool "Build with scan-build for static analysis"
+ default n
help
- This option sets the maximum permissible HyperTransport link width.
- Use of this option will only limit the autodetected HT width; it will not (and cannot) increase the width beyond the autodetected limits.
- This is primarily used to work around poorly designed or laid out HT traces on certain motherboards.
+ Changes the build process to scan-build is used.
+ Requires scan-build in path.
-config LIMIT_HT_UP_WIDTH_8
- bool "8 bits"
-config LIMIT_HT_UP_WIDTH_16
- bool "16 bits"
-endchoice
+config SCANBUILD_REPORT_LOCATION
+ string "Directory to put scan-build report in"
+ default ""
+ depends on SCANBUILD_ENABLE
+ help
+ Where the scan-build report should be stored
+
+config CCACHE
+ bool "ccache"
+ default n
+ help
+ Enables the use of ccache for faster builds.
+ Requires ccache in path.
endmenu
+source src/mainboard/Kconfig
+source src/arch/i386/Kconfig
+
+menu "Chipset"
+
+comment "CPU"
+source src/cpu/Kconfig
+comment "Northbridge"
source src/northbridge/Kconfig
comment "Southbridge"
source src/southbridge/Kconfig
int
default 36
-config XIP_ROM_BASE
- hex
- default 0xfffe0000
-
-config XIP_ROM_SIZE
- hex
- default 0x20000
-
-config LB_CKS_RANGE_START
- int
- default 49
-
-config LB_CKS_RANGE_END
- int
- default 125
-
-config LB_CKS_LOC
- int
- default 126
-
config LOGICAL_CPUS
bool
default y
default n
config USE_OPTION_TABLE
- bool
+ bool "Use CMOS for configuration values"
default n
config MAX_CPUS
bool
default n
-config RAMTOP
- hex
- default 0x200000
-
config ATI_RAGE_XL
bool
int
default 0
-config HAVE_FALLBACK_BOOT
- bool
- default y
-
-config USE_FALLBACK_IMAGE
- bool
- default y
-
-config HAVE_FAILOVER_BOOT
- bool
- default n
-
-config USE_FAILOVER_IMAGE
- bool
- default n
-
config HAVE_HARD_RESET
bool
default y if BOARD_HAS_HARD_RESET
This variable specifies whether a given board has a hard_reset
function, no matter if it's provided by board code or chipset code.
-config BOARD_HAS_HARD_RESET
- bool
- default n
- help
- This variable specifies whether a given board has a reset.c
- file containing a hard_reset() function.
-
-config BOARD_HAS_FADT
- bool
- default n
- help
- This variable specifies whether a given board has a board-local
- FADT in fadt.c. Long-term, those should be moved to appropriate
- chipset components (eg. southbridge)
-
-config HAVE_BUS_CONFIG
- bool
- default n
- help
- This variable specifies whether a given board has a get_bus_conf.c
- file containing bus configuration data.
-
config HAVE_INIT_TIMER
bool
default n if UDELAY_IO
depends on BOOTSPLASH
default "bootsplash.jpg"
help
- The path and filename of the file to use as graphical bootsplash
- screen. The file format has to be jpg.
+ The path and filename of the file to use as graphical bootsplash
+ screen. The file format has to be jpg.
# TODO: Turn this into a "choice".
config FRAMEBUFFER_VESA_MODE
If enabled, you will be able to set breakpoints for gdb debugging.
See src/arch/i386/lib/c_start.S for details.
+config DEBUG_RAM_SETUP
+ bool "Output verbose RAM init debug messages"
+ default n
+ depends on (NORTHBRIDGE_AMD_AMDFAM10 \
+ || NORTHBRIDGE_AMD_AMDK8 \
+ || NORTHBRIDGE_VIA_CN700 \
+ || NORTHBRIDGE_VIA_CX700 \
+ || NORTHBRIDGE_VIA_VX800 \
+ || NORTHBRIDGE_INTEL_E7501 \
+ || NORTHBRIDGE_INTEL_I440BX \
+ || NORTHBRIDGE_INTEL_I82810 \
+ || NORTHBRIDGE_INTEL_I82830 \
+ || NORTHBRIDGE_INTEL_I945)
+ help
+ This option enables additional RAM init related debug messages.
+ It is recommended to enable this when debugging issues on your
+ board which might be RAM init related.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config DEBUG_SMBUS
+ bool "Output verbose SMBus debug messages"
+ default n
+ depends on (SOUTHBRIDGE_VIA_VT8237R \
+ || NORTHBRIDGE_VIA_VX800 \
+ || NORTHBRIDGE_VIA_CX700 \
+ || NORTHBRIDGE_AMD_AMDK8 \
+ || NORTHBRIDGE_AMD_AMDFAM10 \
+ || SOUTHBRIDGE_VIA_VT8231)
+ help
+ This option enables additional SMBus (and SPD) debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config DEBUG_SMI
+ bool "Output verbose SMI debug messages"
+ default n
+ depends on HAVE_SMI_HANDLER
+ help
+ This option enables additional SMI related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG
+ bool "Output verbose x86emu debug messages"
+ default n
+ depends on PCI_OPTION_ROM_RUN_YABEL
+ help
+ This option enables additional x86emu related debug messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_JMP
+ bool "Trace JMP/RETF"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print information about JMP and RETF opcodes from x86emu.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_TRACE
+ bool "Trace all opcodes"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print _all_ opcodes that are executed by x86emu.
+
+ WARNING: This will produce a LOT of output and take a long time.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_PNP
+ bool "Log Plug&Play accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print Plug And Play accesses made by option ROMs.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_DISK
+ bool "Log Disk I/O"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print Disk I/O related messages.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_PMM
+ bool "Log PMM"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to POST Memory Manager (PMM).
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+
+config X86EMU_DEBUG_VBE
+ bool "Debug VESA BIOS Extensions"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to VESA BIOS Extension (VBE) functions.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_INT10
+ bool "Redirect INT10 output to console"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Let INT10 (i.e. character output) calls print messages to debug output.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_INTERRUPTS
+ bool "Log intXX calls"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to interrupt handling.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_CHECK_VMEM_ACCESS
+ bool "Log special memory accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print messages related to accesses to certain areas of the virtual
+ memory (e.g. BDA (BIOS Data Area) or interrupt vectors)
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_MEM
+ bool "Log all memory accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print memory accesses made by option ROM.
+ Note: This also includes accesses to fetch instructions.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config X86EMU_DEBUG_IO
+ bool "Log IO accesses"
+ default n
+ depends on X86EMU_DEBUG
+ help
+ Print I/O accesses made by option ROM.
+
+ Note: This option will increase the size of the coreboot image.
+
+ If unsure, say N.
+
+config LLSHELL
+ bool "Built-in low-level shell"
+ default n
+ help
+ If enabled, you will have a low level shell to examine your machine.
+ Put llshell() in your (romstage) code to start the shell.
+ See src/arch/i386/llshell/llshell.inc for details.
+
endmenu
config LIFT_BSP_APIC_ID
bool
default n
-config USE_INIT
- bool
- default n
-
config ENABLE_APIC_EXT_ID
bool
default n
config ID_SECTION_OFFSET
hex
default 0x10
+
+source src/Kconfig.deprecated_options
projects / coreboot.git / blobdiff