case MONO_TYPE_U4:
case MONO_TYPE_I:
case MONO_TYPE_U:
+ case MONO_TYPE_PTR:
return TRUE;
case MONO_TYPE_OBJECT:
case MONO_TYPE_STRING:
MonoMethodVar *vmv = MONO_VARINFO (cfg, i);
/* unused vars */
- if (vmv->range.first_use.abs_pos > vmv->range.last_use.abs_pos)
+ if (vmv->range.first_use.abs_pos >= vmv->range.last_use.abs_pos)
continue;
if ((ins->flags & (MONO_INST_IS_DEAD|MONO_INST_VOLATILE|MONO_INST_INDIRECT)) ||
if (ins->dreg != ins->sreg1) {
ins->opcode = OP_MOVE;
} else {
- last_ins->next = ins->next;
- ins = ins->next;
+ last_ins->next = ins->next;
+ ins = ins->next;
continue;
}
}
break;
case OP_COMPARE_IMM:
- /* OP_COMPARE_IMM (reg, 0) --> OP_X86_TEST_NULL (reg) */
+ /* OP_COMPARE_IMM (reg, 0)
+ * -->
+ * OP_X86_TEST_NULL (reg)
+ */
if (ins->inst_imm == 0 && ins->next &&
(ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
ins->next->opcode == OP_CEQ)) {
ins->opcode = OP_X86_TEST_NULL;
}
break;
+ case OP_X86_COMPARE_MEMBASE_IMM:
+ /*
+ * OP_STORE_MEMBASE_REG reg, offset(basereg)
+ * OP_X86_COMPARE_MEMBASE_IMM offset(basereg), imm
+ * -->
+ * OP_STORE_MEMBASE_REG reg, offset(basereg)
+ * OP_COMPARE_IMM reg, imm
+ *
+ * Note: if imm = 0 then OP_COMPARE_IMM replaced with OP_X86_TEST_NULL
+ */
+ if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG) &&
+ ins->inst_basereg == last_ins->inst_destbasereg &&
+ ins->inst_offset == last_ins->inst_offset) {
+ ins->opcode = OP_COMPARE_IMM;
+ ins->sreg1 = last_ins->sreg1;
+
+ /* check if we can remove cmp reg,0 with test null */
+ if (ins->inst_imm == 0 && ins->next &&
+ (ins->next->opcode == CEE_BEQ || ins->next->opcode == CEE_BNE_UN ||
+ ins->next->opcode == OP_CEQ)) {
+ ins->opcode = OP_X86_TEST_NULL;
+ }
+ }
+
+ break;
case OP_LOAD_MEMBASE:
case OP_LOADI4_MEMBASE:
/*
- * OP_STORE_MEMBASE_REG reg, offset(basereg)
- * OP_LOAD_MEMBASE offset(basereg), reg
+ * Note: if reg1 = reg2 the load op is removed
+ *
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_LOAD_MEMBASE offset(basereg), reg2
+ * -->
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_MOVE reg1, reg2
*/
if (last_ins && (last_ins->opcode == OP_STOREI4_MEMBASE_REG
|| last_ins->opcode == OP_STORE_MEMBASE_REG) &&
/*
* Note: reg1 must be different from the basereg in the second load
+ * Note: if reg1 = reg2 is equal then second load is removed
+ *
* OP_LOAD_MEMBASE offset(basereg), reg1
* OP_LOAD_MEMBASE offset(basereg), reg2
* -->
break;
case OP_LOADU1_MEMBASE:
case OP_LOADI1_MEMBASE:
- /*
- * FIXME: Missing explanation
- */
+ /*
+ * Note: if reg1 = reg2 the load op is removed
+ *
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_LOAD_MEMBASE offset(basereg), reg2
+ * -->
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_MOVE reg1, reg2
+ */
if (last_ins && (last_ins->opcode == OP_STOREI1_MEMBASE_REG) &&
ins->inst_basereg == last_ins->inst_destbasereg &&
ins->inst_offset == last_ins->inst_offset) {
break;
case OP_LOADU2_MEMBASE:
case OP_LOADI2_MEMBASE:
- /*
- * FIXME: Missing explanation
- */
+ /*
+ * Note: if reg1 = reg2 the load op is removed
+ *
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_LOAD_MEMBASE offset(basereg), reg2
+ * -->
+ * OP_STORE_MEMBASE_REG reg1, offset(basereg)
+ * OP_MOVE reg1, reg2
+ */
if (last_ins && (last_ins->opcode == OP_STOREI2_MEMBASE_REG) &&
ins->inst_basereg == last_ins->inst_destbasereg &&
ins->inst_offset == last_ins->inst_offset) {
case CEE_CONV_I4:
case CEE_CONV_U4:
case OP_MOVE:
- /*
+ /*
+ * Removes:
+ *
* OP_MOVE reg, reg
*/
if (ins->dreg == ins->sreg1) {
continue;
}
/*
+ * Removes:
+ *
* OP_MOVE sreg, dreg
* OP_MOVE dreg, sreg
*/
/* forward pass on the instructions to collect register liveness info */
while (ins) {
spec = ins_spec [ins->opcode];
+
DEBUG (print_ins (i, ins));
if (spec [MONO_INST_SRC1]) {
reginfo1 = reginfo;
reginfo1 [ins->sreg1].prev_use = reginfo1 [ins->sreg1].last_use;
reginfo1 [ins->sreg1].last_use = i;
+ if (spec [MONO_INST_SRC1] == 'L') {
+ /* The virtual register is allocated sequentially */
+ reginfo1 [ins->sreg1 + 1].prev_use = reginfo1 [ins->sreg1 + 1].last_use;
+ reginfo1 [ins->sreg1 + 1].last_use = i;
+ if (reginfo1 [ins->sreg1 + 1].born_in == 0 || reginfo1 [ins->sreg1 + 1].born_in > i)
+ reginfo1 [ins->sreg1 + 1].born_in = i;
+ }
} else {
ins->sreg1 = -1;
}
reginfo2 = reginfo;
reginfo2 [ins->sreg2].prev_use = reginfo2 [ins->sreg2].last_use;
reginfo2 [ins->sreg2].last_use = i;
+ if (spec [MONO_INST_SRC2] == 'L') {
+ /* The virtual register is allocated sequentially */
+ reginfo2 [ins->sreg2 + 1].prev_use = reginfo2 [ins->sreg2 + 1].last_use;
+ reginfo2 [ins->sreg2 + 1].last_use = i;
+ if (reginfo2 [ins->sreg2 + 1].born_in == 0 || reginfo2 [ins->sreg2 + 1].born_in > i)
+ reginfo2 [ins->sreg2 + 1].born_in = i;
+ }
} else {
ins->sreg2 = -1;
}
reginfod [ins->dreg].last_use = i;
if (reginfod [ins->dreg].born_in == 0 || reginfod [ins->dreg].born_in > i)
reginfod [ins->dreg].born_in = i;
- if (spec [MONO_INST_DEST] == 'l') {
- /* result in eax:edx, the virtual register is allocated sequentially */
+ if (spec [MONO_INST_DEST] == 'l' || spec [MONO_INST_DEST] == 'L') {
+ /* The virtual register is allocated sequentially */
reginfod [ins->dreg + 1].prev_use = reginfod [ins->dreg + 1].last_use;
reginfod [ins->dreg + 1].last_use = i;
if (reginfod [ins->dreg + 1].born_in == 0 || reginfod [ins->dreg + 1].born_in > i)
DEBUG (print_regtrack (reginfof, rs->next_vfreg));
tmp = reversed;
while (tmp) {
- int prev_dreg, prev_sreg1, prev_sreg2;
+ int prev_dreg, prev_sreg1, prev_sreg2, clob_dreg;
dest_mask = src1_mask = src2_mask = X86_CALLEE_REGS;
--i;
ins = tmp->data;
spec = ins_spec [ins->opcode];
prev_dreg = -1;
+ clob_dreg = -1;
DEBUG (g_print ("processing:"));
DEBUG (print_ins (i, ins));
if (spec [MONO_INST_CLOB] == 's') {
if (new_dest < 0)
new_dest = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
g_assert (new_dest >= 0);
+ DEBUG (g_print ("\tclob:s changing dreg from R%d to %s (val = %d)\n", ins->dreg, mono_arch_regname (new_dest), val));
+ clob_dreg = ins->dreg;
ins->dreg = new_dest;
create_copy_ins (cfg, X86_ECX, new_dest, ins);
need_ecx_spill = FALSE;
* shift instruction clobbers the first operand.
*/
MonoInst *copy = create_copy_ins (cfg, ins->dreg, val, NULL);
+ DEBUG (g_print ("\tclob:s moved sreg1 from R%d to R%d\n", val, ins->dreg));
insert_before_ins (ins, tmp, copy);
}
val = rs->iassign [ins->sreg2];
fspill_list = g_list_remove (fspill_list, spill_node->data);
fspill--;
}
- }
+ } else if (spec [MONO_INST_DEST] == 'L') {
+ int hreg;
+ val = rs->iassign [ins->dreg];
+ /* check special case when dreg have been moved from ecx (clob shift) */
+ if (spec [MONO_INST_CLOB] == 's' && clob_dreg != -1)
+ hreg = clob_dreg + 1;
+ else
+ hreg = ins->dreg + 1;
+
+ /* base prev_dreg on fixed hreg, handle clob case */
+ prev_dreg = hreg - 1;
+
+ if (val < 0) {
+ int spill = 0;
+ if (val < -1) {
+ /* the register gets spilled after this inst */
+ spill = -val -1;
+ }
+ val = mono_regstate_alloc_int (rs, dest_mask);
+ if (val < 0) /* todo: should we force reg into eax, for opt reasons? */
+ val = get_register_spilling (cfg, tmp, ins, dest_mask, ins->dreg);
+ rs->iassign [ins->dreg] = val;
+ if (spill)
+ create_spilled_store (cfg, spill, val, prev_dreg, ins);
+ }
+
+ DEBUG (g_print ("\tassigned dreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg - 1));
+
+ rs->isymbolic [val] = hreg - 1;
+ ins->dreg = val;
+
+ val = rs->iassign [hreg];
+ if (val < 0) {
+ int spill = 0;
+ if (val < -1) {
+ /* the register gets spilled after this inst */
+ spill = -val -1;
+ }
+ val = mono_regstate_alloc_int (rs, dest_mask);
+ if (val < 0) /* todo: should we force reg into edx, for opt reasons? */
+ val = get_register_spilling (cfg, tmp, ins, dest_mask, hreg);
+ rs->iassign [hreg] = val;
+ if (spill)
+ create_spilled_store (cfg, spill, val, hreg, ins);
+ }
+
+ DEBUG (g_print ("\tassigned hreg (long) %s to dest R%d\n", mono_arch_regname (val), hreg));
+ rs->isymbolic [val] = hreg;
+ /* save reg allocating into unused */
+ ins->unused = val;
+
+ if (reg_is_freeable (val) && hreg >= 0 && reginfo [hreg].born_in >= i) {
+ DEBUG (g_print ("\tfreeable %s (R%d)\n", mono_arch_regname (val), hreg));
+ mono_regstate_free_int (rs, val);
+ }
+ }
else if (ins->dreg >= MONO_MAX_IREGS) {
val = rs->iassign [ins->dreg];
prev_dreg = ins->dreg;
DEBUG (g_print ("\tassigned dreg %s to dest R%d\n", mono_arch_regname (val), ins->dreg));
rs->isymbolic [val] = prev_dreg;
ins->dreg = val;
+ /* handle cases where lreg needs to be eax:edx */
if (spec [MONO_INST_DEST] == 'l') {
int hreg = prev_dreg + 1;
val = rs->iassign [hreg];
}
DEBUG (g_print ("\tassigned hreg %s to dest R%d\n", mono_arch_regname (val), hreg));
rs->isymbolic [val] = hreg;
- /* FIXME:? ins->dreg = val; */
if (ins->dreg == X86_EAX) {
if (val != X86_EDX)
create_copy_ins (cfg, val, X86_EDX, ins);
if (store)
insert_before_ins (load, tmp, store);
}
- }
+ } else if ((spec [MONO_INST_DEST] == 'L') && (spec [MONO_INST_SRC1] == 'L')) {
+ /* force source to be same as dest */
+ rs->iassign [ins->sreg1] = ins->dreg;
+ rs->iassign [ins->sreg1 + 1] = ins->unused;
+
+ DEBUG (g_print ("\tassigned sreg1 (long) %s to sreg1 R%d\n", mono_arch_regname (ins->dreg), ins->sreg1));
+ DEBUG (g_print ("\tassigned sreg1 (long-high) %s to sreg1 R%d\n", mono_arch_regname (ins->unused), ins->sreg1 + 1));
+
+ ins->sreg1 = ins->dreg;
+ /* no need for this, we know that src1=dest in this cases */
+ /*ins->inst_c0 = ins->unused;*/
+
+ /* make sure that we remove them from free mask */
+ rs->ifree_mask &= ~ (1 << ins->dreg);
+ rs->ifree_mask &= ~ (1 << ins->unused);
+ }
else if (ins->sreg1 >= MONO_MAX_IREGS) {
val = rs->iassign [ins->sreg1];
prev_sreg1 = ins->sreg1;
if (cfg->opt & MONO_OPT_PEEPHOLE)
peephole_pass (cfg, bb);
-#if 0
- /*
- * various stratgies to align BBs. Using real loop detection or simply
- * aligning every block leads to more consistent benchmark results,
- * but usually slows down the code
- * we should do the alignment outside this function or we should adjust
- * bb->native offset as well or the code is effectively slowed down!
- */
- /* align all blocks */
-// if ((pad = (cfg->code_len & (align - 1)))) {
- /* poor man loop start detection */
-// if (bb->code && bb->in_count && bb->in_bb [0]->cil_code > bb->cil_code && (pad = (cfg->code_len & (align - 1)))) {
- /* consider real loop detection and nesting level */
-// if (bb->loop_blocks && bb->nesting < 3 && (pad = (cfg->code_len & (align - 1)))) {
- /* consider real loop detection */
- if (bb->loop_blocks && (pad = (cfg->code_len & (align - 1)))) {
- pad = align - pad;
- x86_padding (code, pad);
- cfg->code_len += pad;
- bb->native_offset = cfg->code_len;
+ if (cfg->opt & MONO_OPT_LOOP) {
+ int pad, align = 8;
+ /* set alignment depending on cpu */
+ if (bb->nesting && (bb->in_count == 1) && (pad = (cfg->code_len & (align - 1)))) {
+ pad = align - pad;
+ /*g_print ("adding %d pad at %x to loop in %s\n", pad, cfg->code_len, cfg->method->name);*/
+ x86_padding (code, pad);
+ cfg->code_len += pad;
+ bb->native_offset = cfg->code_len;
+ }
}
-#endif
if (cfg->verbose_level > 2)
g_print ("Basic block %d starting at offset 0x%x\n", bb->block_num, bb->native_offset);
case OP_X86_ADD_MEMBASE_IMM:
x86_alu_membase_imm (code, X86_ADD, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
break;
+ case OP_X86_ADD_MEMBASE:
+ x86_alu_reg_membase (code, X86_ADD, ins->sreg1, ins->sreg2, ins->inst_offset);
+ break;
case OP_X86_SUB_MEMBASE_IMM:
x86_alu_membase_imm (code, X86_SUB, ins->inst_basereg, ins->inst_offset, ins->inst_imm);
break;
+ case OP_X86_SUB_MEMBASE:
+ x86_alu_reg_membase (code, X86_SUB, ins->sreg1, ins->sreg2, ins->inst_offset);
+ break;
case OP_X86_INC_MEMBASE:
x86_inc_membase (code, ins->inst_basereg, ins->inst_offset);
break;
case OP_X86_DEC_REG:
x86_dec_reg (code, ins->dreg);
break;
+ case OP_X86_MUL_MEMBASE:
+ x86_imul_reg_membase (code, ins->sreg1, ins->sreg2, ins->inst_offset);
+ break;
case CEE_BREAK:
x86_breakpoint (code);
break;
case OP_SHL_IMM:
x86_shift_reg_imm (code, X86_SHL, ins->dreg, ins->inst_imm);
break;
+ case OP_LSHL: {
+ guint8 *jump_to_end;
+
+ /* handle shifts below 32 bits */
+ x86_shld_reg (code, ins->unused, ins->sreg1);
+ x86_shift_reg (code, X86_SHL, ins->sreg1);
+
+ x86_test_reg_imm (code, X86_ECX, 32);
+ jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, TRUE);
+
+ /* handle shift over 32 bit */
+ x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
+ x86_clear_reg (code, ins->sreg1);
+
+ x86_patch (jump_to_end, code);
+ }
+ break;
+ case OP_LSHR: {
+ guint8 *jump_to_end;
+
+ /* handle shifts below 32 bits */
+ x86_shrd_reg (code, ins->sreg1, ins->unused);
+ x86_shift_reg (code, X86_SAR, ins->unused);
+
+ x86_test_reg_imm (code, X86_ECX, 32);
+ jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
+
+ /* handle shifts over 31 bits */
+ x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
+ x86_shift_reg_imm (code, X86_SAR, ins->unused, 31);
+
+ x86_patch (jump_to_end, code);
+ }
+ break;
+ case OP_LSHR_UN: {
+ guint8 *jump_to_end;
+
+ /* handle shifts below 32 bits */
+ x86_shrd_reg (code, ins->sreg1, ins->unused);
+ x86_shift_reg (code, X86_SHR, ins->unused);
+
+ x86_test_reg_imm (code, X86_ECX, 32);
+ jump_to_end = code; x86_branch8 (code, X86_CC_EQ, 0, FALSE);
+
+ /* handle shifts over 31 bits */
+ x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
+ x86_shift_reg_imm (code, X86_SHR, ins->unused, 31);
+
+ x86_patch (jump_to_end, code);
+ }
+ break;
+ case OP_LSHL_IMM:
+ if (ins->inst_imm >= 32) {
+ x86_mov_reg_reg (code, ins->unused, ins->sreg1, 4);
+ x86_clear_reg (code, ins->sreg1);
+ x86_shift_reg_imm (code, X86_SHL, ins->unused, ins->inst_imm - 32);
+ } else {
+ x86_shld_reg_imm (code, ins->unused, ins->sreg1, ins->inst_imm);
+ x86_shift_reg_imm (code, X86_SHL, ins->sreg1, ins->inst_imm);
+ }
+ break;
+ case OP_LSHR_IMM:
+ if (ins->inst_imm >= 32) {
+ x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
+ x86_shift_reg_imm (code, X86_SAR, ins->unused, 0x1f);
+ x86_shift_reg_imm (code, X86_SAR, ins->sreg1, ins->inst_imm - 32);
+ } else {
+ x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
+ x86_shift_reg_imm (code, X86_SAR, ins->unused, ins->inst_imm);
+ }
+ break;
+ case OP_LSHR_UN_IMM:
+ if (ins->inst_imm >= 32) {
+ x86_mov_reg_reg (code, ins->sreg1, ins->unused, 4);
+ x86_clear_reg (code, ins->unused);
+ x86_shift_reg_imm (code, X86_SHR, ins->sreg1, ins->inst_imm - 32);
+ } else {
+ x86_shrd_reg_imm (code, ins->sreg1, ins->unused, ins->inst_imm);
+ x86_shift_reg_imm (code, X86_SHR, ins->unused, ins->inst_imm);
+ }
+ break;
case CEE_NOT:
x86_not_reg (code, ins->sreg1);
break;
}
x86_mul_reg (code, non_eax_reg, FALSE);
/* save before the check since pop and mov don't change the flags */
+ if (ins->dreg != X86_EAX)
+ x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
if (saved_edx)
x86_pop_reg (code, X86_EDX);
if (saved_eax)
x86_pop_reg (code, X86_EAX);
- if (ins->dreg != X86_EAX)
- x86_mov_reg_reg (code, ins->dreg, X86_EAX, 4);
EMIT_COND_SYSTEM_EXCEPTION (X86_CC_O, FALSE, "OverflowException");
break;
}
x86_mov_reg_imm (code, ins->dreg, 0);
break;
case CEE_CONV_I4:
- case CEE_CONV_U4:
case OP_MOVE:
x86_mov_reg_reg (code, ins->dreg, ins->sreg1, 4);
break;
+ case CEE_CONV_U4:
+ g_assert_not_reached ();
case CEE_JMP: {
/*
* Note: this 'frame destruction' logic is useful for tail calls, too.
code = emit_float_to_int (cfg, code, ins->dreg, 4, TRUE);
break;
case OP_FCONV_TO_I8:
- /* we defined this instruction to output only to eax:edx */
x86_alu_reg_imm (code, X86_SUB, X86_ESP, 4);
x86_fnstcw_membase(code, X86_ESP, 0);
- x86_mov_reg_membase (code, X86_EAX, X86_ESP, 0, 2);
- x86_alu_reg_imm (code, X86_OR, X86_EAX, 0xc00);
- x86_mov_membase_reg (code, X86_ESP, 2, X86_EAX, 2);
+ x86_mov_reg_membase (code, ins->dreg, X86_ESP, 0, 2);
+ x86_alu_reg_imm (code, X86_OR, ins->dreg, 0xc00);
+ x86_mov_membase_reg (code, X86_ESP, 2, ins->dreg, 2);
x86_fldcw_membase (code, X86_ESP, 2);
x86_alu_reg_imm (code, X86_SUB, X86_ESP, 8);
x86_fist_pop_membase (code, X86_ESP, 0, TRUE);
- x86_pop_reg (code, X86_EAX);
- x86_pop_reg (code, X86_EDX);
+ x86_pop_reg (code, ins->dreg);
+ x86_pop_reg (code, ins->unused);
x86_fldcw_membase (code, X86_ESP, 0);
x86_alu_reg_imm (code, X86_ADD, X86_ESP, 4);
break;
x86_push_reg (code, X86_EAX);
x86_fptan (code);
x86_fnstsw (code);
- x86_test_reg_imm (code, X86_EAX, 0x400);
+ x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
check_pos = code;
x86_branch8 (code, X86_CC_NE, 0, FALSE);
x86_fstp (code, 0); /* pop the 1.0 */
x86_fxch (code, 1);
x86_fprem1 (code);
x86_fstsw (code);
- x86_test_reg_imm (code, X86_EAX, 0x400);
+ x86_test_reg_imm (code, X86_EAX, X86_FP_C2);
pop_jump = code;
x86_branch8 (code, X86_CC_NE, 0, FALSE);
x86_fstp (code, 1);
/* x86_fprem1 (code); */
x86_fprem (code);
x86_fnstsw (code);
- x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x0400);
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_C2);
l2 = code + 2;
x86_branch8 (code, X86_CC_NE, l1 - l2, FALSE);
}
/* this overwrites EAX */
EMIT_FPCOMPARE(code);
- x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
break;
case OP_FCEQ:
if (cfg->opt & MONO_OPT_FCMOV) {
x86_push_reg (code, X86_EAX);
EMIT_FPCOMPARE(code);
- x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
x86_set_reg (code, X86_CC_EQ, ins->dreg, TRUE);
x86_widen_reg (code, ins->dreg, ins->dreg, FALSE, FALSE);
x86_push_reg (code, X86_EAX);
EMIT_FPCOMPARE(code);
- x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
if (ins->opcode == OP_FCLT_UN) {
guchar *is_not_zero_check, *end_jump;
is_not_zero_check = code;
end_jump = code;
x86_jump8 (code, 0);
x86_patch (is_not_zero_check, code);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
x86_patch (end_jump, code);
}
x86_push_reg (code, X86_EAX);
EMIT_FPCOMPARE(code);
- x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4500);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x0100);
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, X86_FP_CC_MASK);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
if (ins->opcode == OP_FCGT_UN) {
guchar *is_not_zero_check, *end_jump;
is_not_zero_check = code;
end_jump = code;
x86_jump8 (code, 0);
x86_patch (is_not_zero_check, code);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
x86_patch (end_jump, code);
}
EMIT_COND_BRANCH (ins, X86_CC_EQ, TRUE);
break;
case OP_FBNE_UN:
+ /* Branch if C013 != 100 */
if (cfg->opt & MONO_OPT_FCMOV) {
- EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
+ /* branch if !ZF or (PF|CF) */
EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
+ EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
+ EMIT_COND_BRANCH (ins, X86_CC_B, FALSE);
break;
}
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4000);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
break;
case OP_FBLT:
end_jump = code;
x86_jump8 (code, 0);
x86_patch (is_not_zero_check, code);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
x86_patch (end_jump, code);
}
EMIT_COND_BRANCH (ins, X86_CC_LT, FALSE);
break;
}
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x0100);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
if (ins->opcode == OP_FBGT_UN) {
guchar *is_not_zero_check, *end_jump;
is_not_zero_check = code;
end_jump = code;
x86_jump8 (code, 0);
x86_patch (is_not_zero_check, code);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x4500);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_CC_MASK);
x86_patch (end_jump, code);
}
EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
break;
case OP_FBGE:
+ /* Branch if C013 == 100 or 001 */
+ if (cfg->opt & MONO_OPT_FCMOV) {
+ guchar *br1;
+
+ /* skip branch if C1=1 */
+ br1 = code;
+ x86_branch8 (code, X86_CC_P, 0, FALSE);
+ /* branch if (C0 | C3) = 1 */
+ EMIT_COND_BRANCH (ins, X86_CC_BE, FALSE);
+ x86_patch (br1, code);
+ break;
+ }
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
+ EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C3);
+ EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
+ break;
case OP_FBGE_UN:
+ /* Branch if C013 == 000 */
if (cfg->opt & MONO_OPT_FCMOV) {
EMIT_COND_BRANCH (ins, X86_CC_LE, FALSE);
break;
EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
break;
case OP_FBLE:
+ /* Branch if C013=000 or 100 */
+ if (cfg->opt & MONO_OPT_FCMOV) {
+ guchar *br1;
+
+ /* skip branch if C1=1 */
+ br1 = code;
+ x86_branch8 (code, X86_CC_P, 0, FALSE);
+ /* branch if C0=0 */
+ EMIT_COND_BRANCH (ins, X86_CC_NB, FALSE);
+ x86_patch (br1, code);
+ break;
+ }
+ x86_alu_reg_imm (code, X86_AND, X86_EAX, (X86_FP_C0|X86_FP_C1));
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0);
+ EMIT_COND_BRANCH (ins, X86_CC_EQ, FALSE);
+ break;
case OP_FBLE_UN:
+ /* Branch if C013 != 001 */
if (cfg->opt & MONO_OPT_FCMOV) {
EMIT_COND_BRANCH (ins, X86_CC_P, FALSE);
EMIT_COND_BRANCH (ins, X86_CC_GE, FALSE);
break;
}
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x0100);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
EMIT_COND_BRANCH (ins, X86_CC_NE, FALSE);
break;
case CEE_CKFINITE: {
x86_fxam (code);
x86_fnstsw (code);
x86_alu_reg_imm (code, X86_AND, X86_EAX, 0x4100);
- x86_alu_reg_imm (code, X86_CMP, X86_EAX, 0x0100);
+ x86_alu_reg_imm (code, X86_CMP, X86_EAX, X86_FP_C0);
x86_pop_reg (code, X86_EAX);
EMIT_COND_SYSTEM_EXCEPTION (X86_CC_EQ, FALSE, "ArithmeticException");
break;
for (patch_info = ji; patch_info; patch_info = patch_info->next) {
unsigned char *ip = patch_info->ip.i + code;
- const unsigned char *target = NULL;
+ const unsigned char *target;
+
+ target = mono_resolve_patch_target (method, domain, code, patch_info, run_cctors);
switch (patch_info->type) {
- case MONO_PATCH_INFO_BB:
- target = patch_info->data.bb->native_offset + code;
- break;
- case MONO_PATCH_INFO_ABS:
- target = patch_info->data.target;
- break;
- case MONO_PATCH_INFO_LABEL:
- target = patch_info->data.inst->inst_c0 + code;
- break;
case MONO_PATCH_INFO_IP:
- *((gpointer *)(ip)) = ip;
+ *((gconstpointer *)(ip)) = target;
continue;
case MONO_PATCH_INFO_METHOD_REL:
- *((gpointer *)(ip)) = code + patch_info->data.offset;
+ *((gconstpointer *)(ip)) = target;
continue;
- case MONO_PATCH_INFO_INTERNAL_METHOD: {
- MonoJitICallInfo *mi = mono_find_jit_icall_by_name (patch_info->data.name);
- if (!mi) {
- g_warning ("unknown MONO_PATCH_INFO_INTERNAL_METHOD %s", patch_info->data.name);
- g_assert_not_reached ();
- }
- target = mono_icall_get_wrapper (mi);
- break;
- }
- case MONO_PATCH_INFO_METHOD_JUMP: {
- GSList *list;
-
- /* get the trampoline to the method from the domain */
- target = mono_create_jump_trampoline (domain, patch_info->data.method, TRUE);
- if (!domain->jump_target_hash)
- domain->jump_target_hash = g_hash_table_new (NULL, NULL);
- list = g_hash_table_lookup (domain->jump_target_hash, patch_info->data.method);
- list = g_slist_prepend (list, ip);
- g_hash_table_insert (domain->jump_target_hash, patch_info->data.method, list);
- break;
- }
- case MONO_PATCH_INFO_METHOD:
- if (patch_info->data.method == method) {
- target = code;
- } else
- /* get the trampoline to the method from the domain */
- target = mono_arch_create_jit_trampoline (patch_info->data.method);
- break;
case MONO_PATCH_INFO_SWITCH: {
- gpointer *jump_table = mono_code_manager_reserve (domain->code_mp, sizeof (gpointer) * patch_info->table_size);
- int i;
-
- *((gconstpointer *)(ip + 2)) = jump_table;
-
- for (i = 0; i < patch_info->table_size; i++) {
- jump_table [i] = code + (int)patch_info->data.table [i];
- }
+ *((gconstpointer *)(ip + 2)) = target;
/* we put into the table the absolute address, no need for x86_patch in this case */
continue;
}
- case MONO_PATCH_INFO_METHODCONST:
- case MONO_PATCH_INFO_CLASS:
- case MONO_PATCH_INFO_IMAGE:
- case MONO_PATCH_INFO_FIELD:
- *((gconstpointer *)(ip + 1)) = patch_info->data.target;
- continue;
case MONO_PATCH_INFO_IID:
- mono_class_init (patch_info->data.klass);
- *((guint32 *)(ip + 1)) = patch_info->data.klass->interface_id;
+ *((guint32 *)(ip + 1)) = (guint32)target;
continue;
- case MONO_PATCH_INFO_VTABLE:
- *((gconstpointer *)(ip + 1)) = mono_class_vtable (domain, patch_info->data.klass);
- continue;
case MONO_PATCH_INFO_CLASS_INIT: {
guint8 *code = ip;
/* Might already been changed to a nop */
x86_call_imm (code, 0);
- target = mono_create_class_init_trampoline (mono_class_vtable (domain, patch_info->data.klass));
break;
}
- case MONO_PATCH_INFO_SFLDA: {
- MonoVTable *vtable = mono_class_vtable (domain, patch_info->data.field->parent);
- if (!vtable->initialized && !(vtable->klass->flags & TYPE_ATTRIBUTE_BEFORE_FIELD_INIT) && mono_class_needs_cctor_run (vtable->klass, method))
- /* Done by the generated code */
- ;
- else {
- if (run_cctors)
- mono_runtime_class_init (vtable);
- }
- *((gconstpointer *)(ip + 1)) =
- (char*)vtable->data + patch_info->data.field->offset;
- continue;
- }
case MONO_PATCH_INFO_R4:
case MONO_PATCH_INFO_R8:
- *((gconstpointer *)(ip + 2)) = patch_info->data.target;
+ *((gconstpointer *)(ip + 2)) = target;
continue;
+ case MONO_PATCH_INFO_METHODCONST:
+ case MONO_PATCH_INFO_CLASS:
+ case MONO_PATCH_INFO_IMAGE:
+ case MONO_PATCH_INFO_FIELD:
+ case MONO_PATCH_INFO_VTABLE:
+ case MONO_PATCH_INFO_SFLDA:
case MONO_PATCH_INFO_EXC_NAME:
- *((gconstpointer *)(ip + 1)) = patch_info->data.name;
- continue;
case MONO_PATCH_INFO_LDSTR:
- *((gconstpointer *)(ip + 1)) =
- mono_ldstr (domain, patch_info->data.token->image,
- mono_metadata_token_index (patch_info->data.token->token));
+ case MONO_PATCH_INFO_TYPE_FROM_HANDLE:
+ case MONO_PATCH_INFO_LDTOKEN:
+ *((gconstpointer *)(ip + 1)) = target;
continue;
- case MONO_PATCH_INFO_TYPE_FROM_HANDLE: {
- gpointer handle;
- MonoClass *handle_class;
-
- handle = mono_ldtoken (patch_info->data.token->image,
- patch_info->data.token->token, &handle_class);
- mono_class_init (handle_class);
- mono_class_init (mono_class_from_mono_type (handle));
-
- *((gconstpointer *)(ip + 1)) =
- mono_type_get_object (domain, handle);
- continue;
- }
- case MONO_PATCH_INFO_LDTOKEN: {
- gpointer handle;
- MonoClass *handle_class;
-
- handle = mono_ldtoken (patch_info->data.token->image,
- patch_info->data.token->token, &handle_class);
- mono_class_init (handle_class);
-
- *((gconstpointer *)(ip + 1)) = handle;
- continue;
- }
default:
- g_assert_not_reached ();
+ break;
}
x86_patch (ip, target);
}
x86_leave (code);
if (CALLCONV_IS_STDCALL (sig->call_convention)) {
- MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
+ MonoJitArgumentInfo *arg_info = alloca (sizeof (MonoJitArgumentInfo) * (sig->param_count + 1));
- stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
- }
- else
- if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
- stack_to_pop = 4;
+ stack_to_pop = mono_arch_get_argument_info (sig, sig->param_count, arg_info);
+ } else if (MONO_TYPE_ISSTRUCT (cfg->method->signature->ret))
+ stack_to_pop = 4;
else
- stack_to_pop = 0;
+ stack_to_pop = 0;
if (stack_to_pop)
x86_ret_imm (code, stack_to_pop);
/* not needed */
}
+void
+mono_arch_flush_register_windows (void)
+{
+}
+
/*
* Support for fast access to the thread-local lmf structure using the GS
* segment register on NPTL + kernel 2.6.x.
void
mono_arch_setup_jit_tls_data (MonoJitTlsData *tls)
{
-#ifndef PLATFORM_WIN32
+#ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
pthread_t self = pthread_self();
pthread_attr_t attr;
void *staddr = NULL;
}
}
-#ifndef PLATFORM_WIN32
+#ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
/* Determine stack boundaries */
if (!mono_running_on_valgrind ()) {
+#ifdef HAVE_PTHREAD_GETATTR_NP
pthread_getattr_np( self, &attr );
+#else
+#ifdef HAVE_PTHREAD_ATTR_GET_NP
+ pthread_attr_get_np( self, &attr );
+#else
+#error "Not implemented"
+#endif
+#endif
pthread_attr_getstack( &attr, &staddr, &stsize );
}
sa.ss_sp = tls->signal_stack;
sa.ss_size = SIGNAL_STACK_SIZE;
sa.ss_flags = SS_ONSTACK;
- sigaltstack (&sa, NULL);
+ sigaltstack (&sa, NULL);
#endif
#ifdef HAVE_KW_THREAD
void
mono_arch_free_jit_tls_data (MonoJitTlsData *tls)
{
-#ifndef PLATFORM_WIN32
+#ifdef MONO_ARCH_SIGSEGV_ON_ALTSTACK
struct sigaltstack sa;
sa.ss_sp = tls->signal_stack;
}
+gboolean
+mono_arch_print_tree (MonoInst *tree, int arity)
+{
+ return 0;
+}
projects / mono.git / blobdiff