* Copyright 2003 Ximian, Inc
* Copyright 2003-2011 Novell Inc
* Copyright 2011 Xamarin Inc
+ * Licensed under the MIT license. See LICENSE file in the project root for full license information.
*/
MINI_OP(OP_LOAD, "load", NONE, NONE, NONE)
MINI_OP(OP_LDADDR, "ldaddr", IREG, NONE, NONE)
MINI_OP(OP_COMPARE, "compare", NONE, IREG, IREG)
MINI_OP(OP_COMPARE_IMM, "compare_imm", NONE, IREG, NONE)
MINI_OP(OP_FCOMPARE, "fcompare", NONE, FREG, FREG)
+MINI_OP(OP_RCOMPARE, "rcompare", NONE, FREG, FREG)
MINI_OP(OP_LCOMPARE, "lcompare", NONE, LREG, LREG)
MINI_OP(OP_ICOMPARE, "icompare", NONE, IREG, IREG)
MINI_OP(OP_ICOMPARE_IMM, "icompare_imm", NONE, IREG, NONE)
MINI_OP(OP_FCALL, "fcall", FREG, NONE, NONE)
MINI_OP(OP_FCALL_REG, "fcall_reg", FREG, IREG, NONE)
MINI_OP(OP_FCALL_MEMBASE, "fcall_membase", FREG, IREG, NONE)
+MINI_OP(OP_RCALL, "rcall", FREG, NONE, NONE)
+MINI_OP(OP_RCALL_REG, "rcall_reg", FREG, IREG, NONE)
+MINI_OP(OP_RCALL_MEMBASE, "rcall_membase", FREG, IREG, NONE)
MINI_OP(OP_LCALL, "lcall", LREG, NONE, NONE)
MINI_OP(OP_LCALL_REG, "lcall_reg", LREG, IREG, NONE)
MINI_OP(OP_LCALL_MEMBASE, "lcall_membase", LREG, IREG, NONE)
MINI_OP(OP_DUMMY_ICONST, "dummy_iconst", IREG, NONE, NONE)
MINI_OP(OP_DUMMY_I8CONST, "dummy_i8const", LREG, NONE, NONE)
MINI_OP(OP_DUMMY_R8CONST, "dummy_r8const", FREG, NONE, NONE)
+MINI_OP(OP_DUMMY_R4CONST, "dummy_r4const", FREG, NONE, NONE)
MINI_OP(OP_DUMMY_VZERO, "dummy_vzero", VREG, NONE, NONE)
MINI_OP(OP_REGVAR, "regvar", NONE, NONE, NONE)
MINI_OP(OP_REGOFFSET, "regoffset", NONE, NONE, NONE)
MINI_OP(OP_LMOVE, "lmove", LREG, LREG, NONE)
MINI_OP(OP_FMOVE, "fmove", FREG, FREG, NONE)
MINI_OP(OP_VMOVE, "vmove", VREG, VREG, NONE)
+MINI_OP(OP_RMOVE, "rmove", FREG, FREG, NONE)
/*
* All 4 of these are only available when soft float isn't active. They
MINI_OP(OP_ICONV_TO_I1,"int_conv_to_i1", IREG, IREG, NONE)
MINI_OP(OP_ICONV_TO_I2,"int_conv_to_i2", IREG, IREG, NONE)
MINI_OP(OP_ICONV_TO_I4,"int_conv_to_i4", IREG, IREG, NONE)
-MINI_OP(OP_ICONV_TO_I8,"int_conv_to_i8", IREG, IREG, NONE)
+MINI_OP(OP_ICONV_TO_I8,"int_conv_to_i8", LREG, IREG, NONE)
MINI_OP(OP_ICONV_TO_R4,"int_conv_to_r4", FREG, IREG, NONE)
MINI_OP(OP_ICONV_TO_R8,"int_conv_to_r8", FREG, IREG, NONE)
MINI_OP(OP_ICONV_TO_U4,"int_conv_to_u4", IREG, IREG, NONE)
MINI_OP(OP_FBLE_UN, "float_ble_un", NONE, NONE, NONE)
MINI_OP(OP_FBLT_UN, "float_blt_un", NONE, NONE, NONE)
+MINI_OP(OP_RBEQ, "r4_beq", NONE, NONE, NONE)
+MINI_OP(OP_RBGE, "r4_bge", NONE, NONE, NONE)
+MINI_OP(OP_RBGT, "r4_bgt", NONE, NONE, NONE)
+MINI_OP(OP_RBLE, "r4_ble", NONE, NONE, NONE)
+MINI_OP(OP_RBLT, "r4_blt", NONE, NONE, NONE)
+MINI_OP(OP_RBNE_UN, "r4_bne_un", NONE, NONE, NONE)
+MINI_OP(OP_RBGE_UN, "r4_bge_un", NONE, NONE, NONE)
+MINI_OP(OP_RBGT_UN, "r4_bgt_un", NONE, NONE, NONE)
+MINI_OP(OP_RBLE_UN, "r4_ble_un", NONE, NONE, NONE)
+MINI_OP(OP_RBLT_UN, "r4_blt_un", NONE, NONE, NONE)
+
/* float opcodes: must be in the same order as the matching CEE_ opcodes: binops_op_map */
MINI_OP(OP_FADD, "float_add", FREG, FREG, FREG)
MINI_OP(OP_FSUB, "float_sub", FREG, FREG, FREG)
MINI_OP(OP_FREM, "float_rem", FREG, FREG, FREG)
MINI_OP(OP_FREM_UN,"float_rem_un", FREG, FREG, FREG)
+/* r4 opcodes: must be in the same order as the matching CEE_ opcodes: binops_op_map */
+MINI_OP(OP_RADD, "r4_add", FREG, FREG, FREG)
+MINI_OP(OP_RSUB, "r4_sub", FREG, FREG, FREG)
+MINI_OP(OP_RMUL, "r4_mul", FREG, FREG, FREG)
+MINI_OP(OP_RDIV, "r4_div", FREG, FREG, FREG)
+MINI_OP(OP_RDIV_UN,"r4_div_un", FREG, FREG, FREG)
+MINI_OP(OP_RREM, "r4_rem", FREG, FREG, FREG)
+MINI_OP(OP_RREM_UN,"r4_rem_un", FREG, FREG, FREG)
+
/* float opcodes: must be in the same order as the matching CEE_ opcodes: unops_op_map */
MINI_OP(OP_FNEG, "float_neg", FREG, FREG, NONE)
MINI_OP(OP_FNOT, "float_not", FREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_U4,"float_conv_to_u4", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_U8,"float_conv_to_u8", LREG, FREG, NONE)
+MINI_OP(OP_RNEG, "r4_neg", FREG, FREG, NONE)
+MINI_OP(OP_RNOT, "r4_not", FREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_I1,"r4_conv_to_i1", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_I2,"r4_conv_to_i2", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_I4,"r4_conv_to_i4", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_I8,"r4_conv_to_i8", LREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_R4,"r4_conv_to_r4", FREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_R8,"r4_conv_to_r8", FREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_U4,"r4_conv_to_u4", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_U8,"r4_conv_to_u8", LREG, FREG, NONE)
+
+/* float opcodes: must be in the same order as the matching CEE_ opcodes: ovfops_op_map */
MINI_OP(OP_FCONV_TO_U2, "float_conv_to_u2", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_U1, "float_conv_to_u1", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_I, "float_conv_to_i", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_I,"float_conv_to_ovf_i", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U,"float_conv_to_ovd_u", IREG, FREG, NONE)
+/* float opcodes: must be in the same order as the matching CEE_ opcodes: ovfops_op_map */
MINI_OP(OP_FADD_OVF, "float_add_ovf", FREG, FREG, FREG)
MINI_OP(OP_FADD_OVF_UN, "float_add_ovf_un", FREG, FREG, FREG)
MINI_OP(OP_FMUL_OVF, "float_mul_ovf", FREG, FREG, FREG)
MINI_OP(OP_FCONV_TO_OVF_I1_UN,"float_conv_to_ovf_i1_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_I2_UN,"float_conv_to_ovf_i2_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_I4_UN,"float_conv_to_ovf_i4_un", IREG, FREG, NONE)
-MINI_OP(OP_FCONV_TO_OVF_I8_UN,"float_conv_to_ovf_i8_un", IREG, FREG, NONE)
+MINI_OP(OP_FCONV_TO_OVF_I8_UN,"float_conv_to_ovf_i8_un", LREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U1_UN,"float_conv_to_ovf_u1_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U2_UN,"float_conv_to_ovf_u2_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U4_UN,"float_conv_to_ovf_u4_un", IREG, FREG, NONE)
-MINI_OP(OP_FCONV_TO_OVF_U8_UN,"float_conv_to_ovf_u8_un", IREG, FREG, NONE)
+MINI_OP(OP_FCONV_TO_OVF_U8_UN,"float_conv_to_ovf_u8_un", LREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_I_UN, "float_conv_to_ovf_i_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U_UN, "float_conv_to_ovf_u_un", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U2,"float_conv_to_ovf_u2", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_I4,"float_conv_to_ovf_i4", IREG, FREG, NONE)
MINI_OP(OP_FCONV_TO_OVF_U4,"float_conv_to_ovf_u4", IREG, FREG, NONE)
-MINI_OP(OP_FCONV_TO_OVF_I8,"float_conv_to_ovf_i8", IREG, FREG, NONE)
-MINI_OP(OP_FCONV_TO_OVF_U8,"float_conv_to_ovf_u8", IREG, FREG, NONE)
+MINI_OP(OP_FCONV_TO_OVF_I8,"float_conv_to_ovf_i8", LREG, FREG, NONE)
+MINI_OP(OP_FCONV_TO_OVF_U8,"float_conv_to_ovf_u8", LREG, FREG, NONE)
/* These do the comparison too */
MINI_OP(OP_FCEQ, "float_ceq", IREG, FREG, FREG)
MINI_OP(OP_FCONV_TO_U, "float_conv_to_u", IREG, FREG, NONE)
MINI_OP(OP_CKFINITE, "ckfinite", FREG, FREG, NONE)
+/* r4 opcodes: must be in the same order as the matching CEE_ opcodes: ovfops_op_map */
+MINI_OP(OP_RCONV_TO_U2, "r4_conv_to_u2", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_U1, "r4_conv_to_u1", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_I, "r4_conv_to_i", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I,"r4_conv_to_ovf_i", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U,"r4_conv_to_ovd_u", IREG, FREG, NONE)
+
+/* r4 opcodes: must be in the same order as the matching CEE_ opcodes: ovfops_op_map */
+MINI_OP(OP_RADD_OVF, "r4_add_ovf", FREG, FREG, FREG)
+MINI_OP(OP_RADD_OVF_UN, "r4_add_ovf_un", FREG, FREG, FREG)
+MINI_OP(OP_RMUL_OVF, "r4_mul_ovf", FREG, FREG, FREG)
+MINI_OP(OP_RMUL_OVF_UN, "r4_mul_ovf_un", FREG, FREG, FREG)
+MINI_OP(OP_RSUB_OVF, "r4_sub_ovf", FREG, FREG, FREG)
+MINI_OP(OP_RSUB_OVF_UN, "r4_sub_ovf_un", FREG, FREG, FREG)
+
+MINI_OP(OP_RCONV_TO_OVF_I1_UN,"r4_conv_to_ovf_i1_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I2_UN,"r4_conv_to_ovf_i2_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I4_UN,"r4_conv_to_ovf_i4_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I8_UN,"r4_conv_to_ovf_i8_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U1_UN,"r4_conv_to_ovf_u1_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U2_UN,"r4_conv_to_ovf_u2_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U4_UN,"r4_conv_to_ovf_u4_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U8_UN,"r4_conv_to_ovf_u8_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I_UN, "r4_conv_to_ovf_i_un", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U_UN, "r4_conv_to_ovf_u_un", IREG, FREG, NONE)
+
+MINI_OP(OP_RCONV_TO_OVF_I1,"r4_conv_to_ovf_i1", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U1,"r4_conv_to_ovf_u1", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I2,"r4_conv_to_ovf_i2", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U2,"r4_conv_to_ovf_u2", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I4,"r4_conv_to_ovf_i4", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U4,"r4_conv_to_ovf_u4", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_I8,"r4_conv_to_ovf_i8", IREG, FREG, NONE)
+MINI_OP(OP_RCONV_TO_OVF_U8,"r4_conv_to_ovf_u8", IREG, FREG, NONE)
+
+/* r4 opcodes: must be in the same order as the matching CEE_ opcodes: ceqops_op_map */
+MINI_OP(OP_RCEQ, "r4_ceq", IREG, FREG, FREG)
+MINI_OP(OP_RCGT, "r4_cgt", IREG, FREG, FREG)
+MINI_OP(OP_RCGT_UN,"r4_cgt_un", IREG, FREG, FREG)
+MINI_OP(OP_RCLT, "r4_clt", IREG, FREG, FREG)
+MINI_OP(OP_RCLT_UN,"r4_clt_un", IREG, FREG, FREG)
+
+MINI_OP(OP_RCNEQ, "r4_cneq", IREG, FREG, FREG)
+MINI_OP(OP_RCGE, "r4_cge", IREG, FREG, FREG)
+MINI_OP(OP_RCLE, "r4_cle", IREG, FREG, FREG)
+
/* Return the low 32 bits of a double vreg */
MINI_OP(OP_FGETLOW32, "float_getlow32", IREG, FREG, NONE)
/* Return the high 32 bits of a double vreg */
MINI_OP(OP_START_HANDLER , "start_handler", NONE, NONE, NONE)
MINI_OP(OP_ENDFILTER, "endfilter", NONE, IREG, NONE)
MINI_OP(OP_ENDFINALLY, "endfinally", NONE, NONE, NONE)
+/*
+ * Returns the exception object passed to catch clauses in
+ * by the EH code in a register.
+ */
+MINI_OP(OP_GET_EX_OBJ, "get_ex_obj", IREG, NONE, NONE)
/* inline (long)int * (long)int */
MINI_OP(OP_BIGMUL, "bigmul", LREG, IREG, IREG)
MINI_OP(OP_PSHLQ_REG, "pshlq_reg", XREG, XREG, XREG)
MINI_OP(OP_EXTRACT_I4, "extract_i4", IREG, XREG, NONE)
+MINI_OP(OP_ICONV_TO_R4_RAW, "iconv_to_r4_raw", FREG, IREG, NONE)
MINI_OP(OP_EXTRACT_I2, "extract_i2", IREG, XREG, NONE)
MINI_OP(OP_EXTRACT_U2, "extract_u2", IREG, XREG, NONE)
*/
MINI_OP(OP_GC_PARAM_SLOT_LIVENESS_DEF, "gc_param_slot_liveness_def", NONE, NONE, NONE)
-/* Arch specific opcodes */
-/* #if defined(__native_client_codegen__) || defined(__native_client__) */
-/* We have to define these in terms of the TARGET defines, not NaCl defines */
-/* because genmdesc.pl doesn't have multiple defines per platform. */
-#if defined(TARGET_AMD64) || defined(TARGET_X86) || defined(TARGET_ARM)
-MINI_OP(OP_NACL_GC_SAFE_POINT, "nacl_gc_safe_point", IREG, NONE, NONE)
-#endif
+MINI_OP(OP_GC_SAFE_POINT, "gc_safe_point", NONE, IREG, NONE)
+/*
+ * Check if the class given by sreg1 was inited, if not, call
+ * mono_generic_class_init_trampoline () though a trampoline.
+ * Since the trampoline saves all registers, this doesn't clobber
+ * any registers.
+ */
+MINI_OP(OP_GENERIC_CLASS_INIT, "generic_class_init", NONE, IREG, NONE)
+
+/* Arch specific opcodes */
#if defined(TARGET_X86) || defined(TARGET_AMD64)
MINI_OP(OP_X86_TEST_NULL, "x86_test_null", NONE, IREG, NONE)
MINI_OP(OP_X86_COMPARE_MEMBASE_REG,"x86_compare_membase_reg", NONE, IREG, IREG)