static const int regbank_size [] = {
MONO_MAX_IREGS,
MONO_MAX_FREGS,
+ MONO_MAX_IREGS,
+ MONO_MAX_IREGS,
MONO_MAX_XREGS
};
static const int regbank_load_ops [] = {
OP_LOADR_MEMBASE,
OP_LOADR8_MEMBASE,
+ OP_LOADR_MEMBASE,
+ OP_LOADR_MEMBASE,
OP_LOADX_MEMBASE
};
static const int regbank_store_ops [] = {
OP_STORER_MEMBASE_REG,
OP_STORER8_MEMBASE_REG,
+ OP_STORER_MEMBASE_REG,
+ OP_STORER_MEMBASE_REG,
OP_STOREX_MEMBASE
};
static const int regbank_move_ops [] = {
OP_MOVE,
OP_FMOVE,
+ OP_MOVE,
+ OP_MOVE,
OP_XMOVE
};
static const regmask_t regbank_callee_saved_regs [] = {
MONO_ARCH_CALLEE_SAVED_REGS,
MONO_ARCH_CALLEE_SAVED_FREGS,
+ MONO_ARCH_CALLEE_SAVED_REGS,
+ MONO_ARCH_CALLEE_SAVED_REGS,
MONO_ARCH_CALLEE_SAVED_XREGS,
};
static const regmask_t regbank_callee_regs [] = {
MONO_ARCH_CALLEE_REGS,
MONO_ARCH_CALLEE_FREGS,
+ MONO_ARCH_CALLEE_REGS,
+ MONO_ARCH_CALLEE_REGS,
MONO_ARCH_CALLEE_XREGS,
};
static const int regbank_spill_var_size[] = {
sizeof (mgreg_t),
sizeof (double),
+ sizeof (mgreg_t),
+ sizeof (mgreg_t),
16 /*FIXME make this a constant. Maybe MONO_ARCH_SIMD_VECTOR_SIZE? */
};
memset (rs->isymbolic, 0, MONO_MAX_IREGS * sizeof (rs->isymbolic [0]));
memset (rs->fsymbolic, 0, MONO_MAX_FREGS * sizeof (rs->fsymbolic [0]));
- rs->symbolic [0] = rs->isymbolic;
- rs->symbolic [1] = rs->fsymbolic;
+ rs->symbolic [MONO_REG_INT] = rs->isymbolic;
+ rs->symbolic [MONO_REG_DOUBLE] = rs->fsymbolic;
#ifdef MONO_ARCH_NEED_SIMD_BANK
memset (rs->xsymbolic, 0, MONO_MAX_XREGS * sizeof (rs->xsymbolic [0]));
- rs->symbolic [2] = rs->xsymbolic;
+ rs->symbolic [MONO_REG_SIMD] = rs->xsymbolic;
#endif
}
{
if (G_UNLIKELY (bank)) {
#if MONO_ARCH_NEED_SIMD_BANK
- if (bank == 2)
+ if (bank == MONO_REG_SIMD)
return mono_arch_xregname (reg);
#endif
- g_assert (bank == 1);
+ if (bank == MONO_REG_INT_REF || bank == MONO_REG_INT_MP)
+ return mono_arch_regname (reg);
+ g_assert (bank == MONO_REG_DOUBLE);
return mono_arch_fregname (reg);
} else {
return mono_arch_regname (reg);
}
}
+/*
+ * mono_call_inst_add_outarg_vt:
+ *
+ * Register OUTARG_VT as belonging to CALL.
+ */
+void
+mono_call_inst_add_outarg_vt (MonoCompile *cfg, MonoCallInst *call, MonoInst *outarg_vt)
+{
+ call->outarg_vts = g_slist_append_mempool (cfg->mempool, call->outarg_vts, outarg_vt);
+}
+
static void
resize_spill_info (MonoCompile *cfg, int bank)
{
g_assert (bank < MONO_NUM_REGBANKS);
- new_info = mono_mempool_alloc (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
+ new_info = mono_mempool_alloc0 (cfg->mempool, sizeof (MonoSpillInfo) * new_len);
if (orig_info)
memcpy (new_info, orig_info, sizeof (MonoSpillInfo) * orig_len);
for (i = orig_len; i < new_len; ++i)
case OP_VCALL2_MEMBASE:
case OP_VOIDCALL:
case OP_VOIDCALL_MEMBASE:
- case OP_VOIDCALLVIRT: {
+ case OP_VOIDCALLVIRT:
+ case OP_TAILCALL: {
MonoCallInst *call = (MonoCallInst*)ins;
GSList *list;
break;
case OP_LIVERANGE_START:
case OP_LIVERANGE_END:
+ case OP_GC_LIVENESS_DEF:
+ case OP_GC_LIVENESS_USE:
printf (" R%d", (int)ins->inst_c1);
break;
+ case OP_SEQ_POINT:
+ printf (" il: %x", (int)ins->inst_imm);
+ break;
default:
break;
}
*last = to_insert;
}
+static inline int
+get_vreg_bank (MonoCompile *cfg, int reg, int bank)
+{
+ if (vreg_is_ref (cfg, reg))
+ return MONO_REG_INT_REF;
+ else if (vreg_is_mp (cfg, reg))
+ return MONO_REG_INT_MP;
+ else
+ return bank;
+}
+
/*
* Force the spilling of the variable in the symbolic register 'reg', and free
* the hreg it was assigned to.
MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
load->dreg = sel;
load->inst_basereg = cfg->frame_reg;
- load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
+ load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, reg, bank));
insert_after_ins (bb, ins, last, load);
DEBUG (printf ("SPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
if (G_UNLIKELY (bank))
MONO_INST_NEW (cfg, load, regbank_load_ops [bank]);
load->dreg = sel;
load->inst_basereg = cfg->frame_reg;
- load->inst_offset = mono_spillvar_offset (cfg, spill, bank);
+ load->inst_offset = mono_spillvar_offset (cfg, spill, get_vreg_bank (cfg, i, bank));
insert_after_ins (bb, ins, last, load);
DEBUG (printf ("\tSPILLED LOAD (%d at 0x%08lx(%%ebp)) R%d (freed %s)\n", spill, (long)load->inst_offset, i, mono_regname_full (sel, bank)));
if (G_UNLIKELY (bank))
free_up_hreg (MonoCompile *cfg, MonoBasicBlock *bb, MonoInst **last, MonoInst *ins, int hreg, int bank)
{
if (G_UNLIKELY (bank)) {
- if (!(cfg->rs->free_mask [1] & (regmask (hreg)))) {
+ if (!(cfg->rs->free_mask [bank] & (regmask (hreg)))) {
bank = translate_bank (cfg->rs, bank, hreg);
DEBUG (printf ("\tforced spill of R%d\n", cfg->rs->symbolic [bank] [hreg]));
spill_vreg (cfg, bb, last, ins, cfg->rs->symbolic [bank] [hreg], bank);
return copy;
}
-static MonoInst*
-create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, int bank)
+static inline const char*
+regbank_to_string (int bank)
+{
+ if (bank == MONO_REG_INT_REF)
+ return "REF ";
+ else if (bank == MONO_REG_INT_MP)
+ return "MP ";
+ else
+ return "";
+}
+
+static void
+create_spilled_store (MonoCompile *cfg, MonoBasicBlock *bb, int spill, int reg, int prev_reg, MonoInst **last, MonoInst *ins, MonoInst *insert_before, int bank)
{
- MonoInst *store;
+ MonoInst *store, *def;
+
+ bank = get_vreg_bank (cfg, prev_reg, bank);
+
MONO_INST_NEW (cfg, store, regbank_store_ops [bank]);
store->sreg1 = reg;
store->inst_destbasereg = cfg->frame_reg;
if (ins) {
mono_bblock_insert_after_ins (bb, ins, store);
*last = store;
+ } else if (insert_before) {
+ insert_before_ins (bb, insert_before, store);
+ } else {
+ g_assert_not_reached ();
+ }
+ DEBUG (printf ("\t%sSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", regbank_to_string (bank), spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
+
+ if (((bank == MONO_REG_INT_REF) || (bank == MONO_REG_INT_MP)) && cfg->compute_gc_maps) {
+ g_assert (prev_reg != -1);
+ MONO_INST_NEW (cfg, def, OP_GC_SPILL_SLOT_LIVENESS_DEF);
+ def->inst_c0 = spill;
+ def->inst_c1 = bank;
+ mono_bblock_insert_after_ins (bb, store, def);
}
- DEBUG (printf ("\tSPILLED STORE (%d at 0x%08lx(%%ebp)) R%d (from %s)\n", spill, (long)store->inst_offset, prev_reg, mono_regname_full (reg, bank)));
- return store;
}
/* flags used in reginfo->flags */
int fpstack [8];
int sp = 0;
#endif
- int num_sregs;
+ int num_sregs = 0;
int sregs [MONO_MAX_SRC_REGS];
if (!bb->code)
local_copy_prop (cfg, ins);*/
i = 1;
- DEBUG (printf ("\nLOCAL REGALLOC: BASIC BLOCK %d:\n", bb->block_num));
+ DEBUG (printf ("\nLOCAL REGALLOC BLOCK %d:\n", bb->block_num));
/* forward pass on the instructions to collect register liveness info */
MONO_BB_FOR_EACH_INS (bb, ins) {
spec = ins_get_spec (ins->opcode);
if (need_assign) {
if (rs->vassign [sreg] < -1) {
- MonoInst *store;
int spill;
/* Need to emit a spill store */
spill = - rs->vassign [sreg] - 1;
- store = create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, bank);
- insert_before_ins (bb, ins, store);
+ create_spilled_store (cfg, bb, spill, dest_sreg, sreg, tmp, NULL, ins, bank);
}
/* force-set sreg2 */
assign_reg (cfg, rs, sregs [j], dest_sreg, 0);
val = alloc_reg (cfg, bb, tmp, ins, dreg_mask, ins->dreg, ®info [ins->dreg], bank);
assign_reg (cfg, rs, ins->dreg, val, bank);
if (spill)
- create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, bank);
+ create_spilled_store (cfg, bb, spill, val, prev_dreg, tmp, ins, NULL, bank);
}
DEBUG (printf ("\tassigned dreg %s to dest R%d\n", mono_regname_full (val, bank), ins->dreg));
if (val < 0)
val = get_register_spilling (cfg, bb, tmp, ins, mask, reg2, bank);
if (spill)
- create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, bank);
+ create_spilled_store (cfg, bb, spill, val, reg2, tmp, ins, NULL, bank);
}
else {
if (! (mask & (regmask (val)))) {
DEBUG (printf ("\tassigned sreg1 %s to R%d\n", mono_regname_full (val, bank), sregs [0]));
if (spill) {
- MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, bank);
/*
* Need to insert before the instruction since it can
* overwrite sreg1.
*/
- insert_before_ins (bb, ins, store);
+ create_spilled_store (cfg, bb, spill, val, prev_sregs [0], tmp, NULL, ins, bank);
}
}
else if ((dest_sregs [0] != -1) && (dest_sregs [0] != val)) {
assign_reg (cfg, rs, sregs [j], val, bank);
DEBUG (printf ("\tassigned sreg%d %s to R%d\n", j + 1, mono_regname_full (val, bank), sregs [j]));
if (spill) {
- MonoInst *store = create_spilled_store (cfg, bb, spill, val, prev_sregs [j], tmp, NULL, bank);
/*
* Need to insert before the instruction since it can
* overwrite sreg2.
*/
- insert_before_ins (bb, ins, store);
+ create_spilled_store (cfg, bb, spill, val, sregs [j], tmp, NULL, ins, bank);
}
}
sregs [j] = val;
switch (cmp_opcode) {
case OP_ICOMPARE:
case OP_ICOMPARE_IMM:
- case OP_LCOMPARE_IMM:
return CMP_TYPE_I;
default:
return CMP_TYPE_L;
return FALSE;
case MONO_TYPE_VALUETYPE:
return FALSE;
+ default:
+ return FALSE;
}
- return FALSE;
}
#ifndef DISABLE_JIT
* OP_STORE_MEMBASE_REG reg1, offset(basereg)
* OP_MOVE reg1, reg2
*/
+ if (last_ins && last_ins->opcode == OP_GC_LIVENESS_DEF)
+ last_ins = last_ins->prev;
if (last_ins &&
(((ins->opcode == OP_LOADI4_MEMBASE) && (last_ins->opcode == OP_STOREI4_MEMBASE_REG)) ||
((ins->opcode == OP_LOAD_MEMBASE) && (last_ins->opcode == OP_STORE_MEMBASE_REG))) &&
projects / mono.git / blobdiff